Standard Cell Library based Memory Compiler using DFF cells
The objective of this project is to develop DFF-based RAM and Register File (RegF) compiler that utilizes standard cell libraries following a standard ASIC implementation approach. The compiler generates different views (HDL netlist, HDL functional models, LEF, GDS, Timing, …) for a given configuration set.
The layout generated from the compiler will be highly compacted (we target over 95% placement density) as the cells are placed on the floor plan using a custom placer. Moreover, the custom placer ensures that the routing will be a seamless one. The project will consider the creation of a custom router if automatic routing using open-source global and detailed routers does not give good results.
Currenly, the repo has only a handcrafted parameterized memory (1, 2 or 4 kbytes) targeting the SKY130 PDK. Also, it contains all the building blocks and a self-checking testbench.
Two modules (single RW port RAM) are provided:
- DFFRAM: parameterized 1 (256x32), 2 (512x32) or 4 (1024x32) kbytes memory module.
- DFFRAM_256x32: 1kbyte memory module
| Port | Direction | Size | Function |
|---|---|---|---|
| CLK | input | 1 | Clock (positive edge triggered) |
| EN | input | 1 | Memory enable. Do is 0 when memory is disabled |
| WE | input | 4 | Write enable (byte level) |
| A | input | 8, 9, 10 | Address lines |
| Di | input | 32 | Data in |
| Do | output | 32 | Data out |
The following waveform diagram shows memory write and read transactions.
To perform a memory write, the memory has to be enabled (EN=1), WE must be set to reflect the bytes to be written, A has the address of the word that contains the bytes to be written and Di has the data to be written. The write will rake place with the positive edge of the clock. To read from the memory, the memory has to be enabled, WE lines must be cleared and A has the memory address. The read word will be available on the Do lines immediately after the positive edge of the clock.
Note: Do lines are set to 0s when EN=0
This file contains a self checking testbench that can be simulated using Icarus Verilog. Also, it contains a behavioral model for the memory.
To run the simulation, you need to have the SKY130 open PDK installed. A makefile is provided to run the simulation.
Untill the compiler is ready, you may use OpenLANE to harden the memory. Make sure that the flow configuration parameter SYNTH_READ_BLACKBOX_LIB is set to 1. A smaple OpenLANE design configuration file can be found here.
The following table compares the hardened handcrafted memories to the equivalent hardened RTL synthesized memories. Both hardened using OpenLANE.
| Memory Type | No. of Instances | Placement Density | Dimensions X (um) x Y (um) |
|---|---|---|---|
| HC 1 kbyte | 19,897 | 87.2% | 425 x 820 |
| HC 2 kbytes | 40,554 | 84.8% | 1,210 x 610 |
| HC 4 kbytes | 81,044 | 84.8% | 1,628 x 911 |
| RTL 1 kbyte | 51,972 | 61% | 1,050 x 1,060 |
| RTL 2 kbytes* | 103,933 | 61% | 1,470 x 1,481 |
| RTL 4 kbytes | 207,822 | 61% | 2,074 x 2,085 |
* OpenLANE did not produce a clean GDSII
We target above 95% placement density using the DDFRAM compiler custom placer.