diff --git a/_index.md b/_index.md index aa521c098a205..ccb5648214f69 100644 --- a/_index.md +++ b/_index.md @@ -28,10 +28,13 @@ Unless otherwise noted, everything in the repository is covered by the Apache Li * User Guides * Reference Manuals * Security -* [Hardware Specifications]({{< relref "hw" >}}) - * Top-level SoC - * Ibex processor core - * Comportable IP blocks +* [Hardware Dashboard]({{< relref "hw" >}}) + * Design specifications + * Verification plans + * Results of tool-flows + * Comportable IPs + * Processor cores + * Top level designs * [Software]({{< relref "sw" >}}) * READMEs of OpenTitan software * [Tools]({{< relref "util" >}}) diff --git a/doc/_index.md b/doc/_index.md index 77d0219dbb87f..6e6be5c600cd5 100644 --- a/doc/_index.md +++ b/doc/_index.md @@ -2,7 +2,11 @@ * [Project]({{< relref "doc/project" >}}) * How the OpenTitan project is organized - * Progress tracking + * Hardware development stages + * Hardware signoff checklist + * Governance + * RFC process + * Committers * [User Guides]({{< relref "doc/ug" >}}) * How to get started with the repo * How to emulate on an FPGA diff --git a/doc/project/_index.md b/doc/project/_index.md index e466b9e175eb6..8985af852e10f 100644 --- a/doc/project/_index.md +++ b/doc/project/_index.md @@ -9,7 +9,7 @@ More information will be added over time. ## Quality standards for open hardware IP In order to gauge the quality of the different IP that is in our repository, we define a series of [Hardware Development Stages]({{< relref "hw_stages" >}}) to track the designs. -The current status of different IP is reflected in the [HW Development Stages Dashboard]({{< relref "hw_dashboard" >}}). +The current status of different IP is reflected in the [Hardware Dashboard]({{< relref "hw" >}}). The final state for developed IP is *Signed Off*, indicating that design and verification is complete, and the IP should be bug free. To make it to that stage, a [Hardware Signoff Checklist]({{< relref "checklist.md" >}}) is used to confirm completion. [Here](https://github.com/lowRISC/opentitan/blob/master/doc/project/ip_checklist.md.tpl) is a template that can be used as a checklist item. diff --git a/doc/project/hw_dashboard.md b/doc/project/hw_dashboard.md deleted file mode 100644 index ace3f6e9aac57..0000000000000 --- a/doc/project/hw_dashboard.md +++ /dev/null @@ -1,8 +0,0 @@ -# Hardware Designs Dashboard - -This dashboard gives the current status of -[Comportable](/doc/rm/comportability_specification) -designs within the OpenTitan project. -See the [Hardware Development Stages]({{< relref "/doc/project/hw_stages.md" >}}) for description of the hardware stages and how they are determined. - -{{< dashboard "hw/ip" >}} diff --git a/doc/project/hw_stages.md b/doc/project/hw_stages.md index 2ff51a820a697..98bb6b2a3c4bc 100644 --- a/doc/project/hw_stages.md +++ b/doc/project/hw_stages.md @@ -6,7 +6,7 @@ This document describes development stages for hardware within the OpenTitan pro This includes design and verification stages meant to give a high-level view of the status of a design. OpenTitan being an open-source program aimed at a high quality silicon release, the intent is to find a balance between the rigor of a heavy tapeout process and the more fluid workings of an open source development. -This document also serves as a guide to the [hardware design dashboard]({{< relref "doc/project/hw_dashboard" >}}), which gives the status of all of the designs in the OpenTitan repository. +This document also serves as a guide to the [Hardware Dashboard]({{< relref "hw" >}}), which gives the status of all of the designs in the OpenTitan repository. This document aims to mostly give a more defined structure to the process that is already followed. Proper versioning of RTL designs is a complex topic. @@ -150,12 +150,12 @@ For example, `file: gpio.prj.hjson`: ```hjson { - name: "gpio", - version: 1.0, - life_stage: "L1", - design_stage: "D2", - verification_stage: "V1", - notes: "information shown on the dashboard" + name: "gpio" + version: 1.0 + life_stage: "L1" + design_stage: "D2" + verification_stage: "V1" + notes: "information shown on the dashboard" } ``` @@ -167,13 +167,27 @@ The commit ID has its own entry in the project Hjson file, as shown below. ```hjson { - name: "gpio", - version: 1.0, - life_stage: "L1", - design_stage: "D2", - verification_stage: "V1", - commit_id: "92e4298f8c2de268b2420a2c16939cd0784f1bf8", - notes: "information shown on the dashboard" + name: "gpio" + version: 1.0 + life_stage: "L1" + design_stage: "D2" + verification_stage: "V1" + commit_id: "92e4298f8c2de268b2420a2c16939cd0784f1bf8" + notes: "information shown on the dashboard" +} +``` + +### Other optional fields + +Additionally, the tool that generates the dashboard accepts the following optional fields: the design specification, the DV plan and the checklist. +They are set as partial paths (reference relative to the top of the repository) to the respective documents as shown below. +They are converted to complete URLs in the generated dashboard. + +```hjson +{ + design_spec: "hw/ip/gpio/doc" + dv_plan: "hw/ip/gpio/doc/dv_plan" + checklist: "hw/ip/gpio/doc/checklist" } ``` @@ -240,4 +254,4 @@ The subject will be revisited as we get closer to locking down the design to tak The stages are reported externally via a script-generated table exposed on the external website. This status is a summary of all `prj.hjson` files of all designs in the system, with multiple lines where there are multiple versions. -The link to that table is [here]({{< relref "doc/project/hw_dashboard" >}}). +The link to that table is [here]({{< relref "hw" >}}). diff --git a/doc/project/ip_checklist.md.tpl b/doc/project/ip_checklist.md.tpl index 585f61b9fa9c9..d40e8ea3c2048 100644 --- a/doc/project/ip_checklist.md.tpl +++ b/doc/project/ip_checklist.md.tpl @@ -2,6 +2,11 @@ title: "${name.upper()} Checklist" --- + This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [${name.upper()} peripheral.]({{< relref "hw/ip/${name}/doc" >}}) All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}}) diff --git a/hw/_index.md b/hw/_index.md index 8952cbb59a18a..52ae476e450d4 100644 --- a/hw/_index.md +++ b/hw/_index.md @@ -1,35 +1,43 @@ -# Hardware Specifications - -This is the landing spot for all hardware specifications within the OpenTitan project. -This includes: top level specification(s); processor core(s) specifications; and [Comportable IP]({{< relref "doc/rm/comportability_specification" >}}) specifications. - -## Available Top Level Specifications - -* [`top_earlgrey` design specification]({{< relref "hw/top_earlgrey/doc" >}}) - -## Available Processor Core Specifications - -* [`core_ibex` user manual](https://ibex-core.readthedocs.io/en/latest) - -## Available Comportable IP Block Design Specifications and Verification Plans - -| Module | Design Spec | DV Plan | -|--------|-------------|---------| -| `aes` | [design spec]({{< relref "hw/ip/aes/doc" >}}) | [DV plan]({{< relref "hw/ip/aes/doc/dv_plan" >}}) | -| `alert_handler` | [design spec]({{< relref "hw/ip/alert_handler/doc" >}}) | [DV plan]({{< relref "hw/ip/alert_handler/doc/dv_plan" >}}) | -| `entropy_src` | [design spec]({{< relref "hw/ip/entropy_src/doc" >}}) | | -| `flash_ctrl` | [design spec]({{< relref "hw/ip/flash_ctrl/doc" >}}) | | -| `gpio` | [design spec]({{< relref "hw/ip/gpio/doc" >}}) | [DV plan]({{< relref "hw/ip/gpio/doc/dv_plan" >}}) | -| `hmac` | [design spec]({{< relref "hw/ip/hmac/doc" >}}) | [DV plan]({{< relref "hw/ip/hmac/doc/dv_plan" >}}) | -| `i2c` | [design spec]({{< relref "hw/ip/i2c/doc" >}}) | [DV plan]({{< relref "hw/ip/i2c/doc/dv_plan" >}}) | -| `nmi_gen` | [design spec]({{< relref "hw/ip/nmi_gen/doc" >}}) | | -| `padctrl` | [design spec]({{< relref "hw/ip/padctrl/doc" >}}) | | -| `pinmux` | [design spec]({{< relref "hw/ip/pinmux/doc" >}}) | | -| `rv_core_ibex` | [design spec]({{< relref "hw/ip/rv_core_ibex/doc" >}}) | | -| `rv_dm` | [design spec]({{< relref "hw/ip/rv_dm/doc" >}}) | | -| `rv_plic` | [design spec]({{< relref "hw/ip/rv_plic/doc" >}}) | [DV plan]({{< relref "hw/ip/rv_plic/doc/dv_plan" >}}) | -| `rv_timer` | [design spec]({{< relref "hw/ip/rv_timer/doc" >}}) | [DV plan]({{< relref "hw/ip/rv_timer/doc/dv_plan" >}}) | -| `spi_device` | [design spec]({{< relref "hw/ip/spi_device/doc" >}}) | [DV plan]({{< relref "hw/ip/spi_device/doc/dv_plan" >}}) | -| `tlul` | [design spec]({{< relref "hw/ip/tlul/doc" >}}) | [DV plan]({{< relref "hw/ip/tlul/doc/dv_plan" >}}) -| `uart` | [design spec]({{< relref "hw/ip/uart/doc" >}}) | [DV plan]({{< relref "hw/ip/uart/doc/dv_plan" >}}) | -| `usbdev` | [design spec]({{< relref "hw/ip/usbdev/doc" >}}) | [DV plan]({{< relref "hw/ip/usbdev/doc/dv_plan" >}}) | +--- +title: "Hardware Dashboard" +--- + +This page serves as the landing spot for all hardware development within the OpenTitan project. + +We start off by providing links to the [results of various tool-flows](#toolflows-summary-results) run on all of our [Comportable]({{< relref "doc/rm/comportability_specification" >}}) IPs. +This includes DV simulations, FPV and lint, all of which are run with the `dvsim` tool which serves as the common frontend. + +The [Comportable IPs](#comportable-ips) following it provides links to their design specifications and DV plans, and tracks their current stage of development. +See the [Hardware Development Stages]({{< relref "/doc/project/hw_stages.md" >}}) for description of the hardware stages and how they are determined. + +Next, we focus on all available [processor cores](#processor-cores) and provide links to their design specifications, DV plans and the DV simulation results. + +Finally, we provide the same set of information for all available [top level designs](#top-level-designs). We may eventually also include the synthesis results for those top level designs. + + +## Results of tool-flows + +* [DV simulation summary results, with coverage (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/summary.html) +* FPV summary results (nightly) (TBD) +* [Lint summary results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/ascentlint/summary.html) + +## Comportable IPs + +{{< dashboard "hw/ip" >}} + +## Processor cores + +* `core_ibex` + * [User manual](https://ibex-core.readthedocs.io/en/latest) + * [DV plan](https://ibex-core.readthedocs.io/en/latest/verification.html) + * DV simulation results, with coverage (nightly) (TBD) + +## Top level designs + +* `top_earlgrey` + * [Design specification]({{< relref "hw/top_earlgrey/doc" >}}) + * DV plan (TBD) + * [DV simulation results, with coverage (nightly)](https://reports.opentitan.org/hw/top_earlgrey/dv/latest/results.html) + * FPV results (nightly) (TBD) + * [Lint results (nightly)](https://reports.opentitan.org/hw/top_earlgrey/lint/latest/results.html) + * Synthesis results (nightly) (TBD) diff --git a/hw/dv/doc/dv_plan_template.md b/hw/dv/doc/dv_plan_template.md index 5bfb43ce96e01..1e5997948120d 100644 --- a/hw/dv/doc/dv_plan_template.md +++ b/hw/dv/doc/dv_plan_template.md @@ -19,9 +19,9 @@ applicable. Once done, remove this comment before making a PR. --> * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) -* DV regression results dashboard (link TBD) +* [Simulation results](https://reports.opentitan.org/hw/ip/foo/dv/latest/results.html) ## Design features diff --git a/hw/ip/aes/data/aes.prj.hjson b/hw/ip/aes/data/aes.prj.hjson index 98ba6cafa0c4c..e2678632095d4 100644 --- a/hw/ip/aes/data/aes.prj.hjson +++ b/hw/ip/aes/data/aes.prj.hjson @@ -4,6 +4,9 @@ { name: "aes", + design_spec: "hw/ip/aes/doc", + dv_plan: "hw/ip/aes/doc/dv_plan", + checklist: "hw/ip/aes/doc/checklist", version: "0.6", life_stage: "L1", design_stage: "D2", diff --git a/hw/ip/aes/doc/dv_plan/index.md b/hw/ip/aes/doc/dv_plan/index.md index d06b4d919d283..1fe74714dcbb7 100644 --- a/hw/ip/aes/doc/dv_plan/index.md +++ b/hw/ip/aes/doc/dv_plan/index.md @@ -10,7 +10,7 @@ title: "AES DV Plan" * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/aes/dv/latest/results.html) diff --git a/hw/ip/alert_handler/data/alert_handler.prj.hjson b/hw/ip/alert_handler/data/alert_handler.prj.hjson index 8b6d02543783c..d84073c2c1ca9 100644 --- a/hw/ip/alert_handler/data/alert_handler.prj.hjson +++ b/hw/ip/alert_handler/data/alert_handler.prj.hjson @@ -4,6 +4,9 @@ { name: "alert_handler", + design_spec: "hw/ip/alert_handler/doc", + dv_plan: "hw/ip/alert_handler/doc/dv_plan", + checklist: "hw/ip/alert_handler/doc/checklist", version: "0.5", life_stage: "L1", design_stage: "D1", diff --git a/hw/ip/alert_handler/doc/checklist.md b/hw/ip/alert_handler/doc/checklist.md index 8a007dd37c2ff..aa14b74eb46f8 100644 --- a/hw/ip/alert_handler/doc/checklist.md +++ b/hw/ip/alert_handler/doc/checklist.md @@ -103,7 +103,7 @@ Review | Signoff date | Not Started | ## Verification Checklist -### Checklists for milestone V1 +### V1 Type | Item | Resolution | Note/Collaterals --------------|---------------------------------------|-------------|------------------ @@ -153,7 +153,7 @@ Review | Signoff date | Not Started | [STD_TEST_CATEGORIES_PLANNED]: {{}} [V2_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V2 +### V2 Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------------|-------------|------------------ @@ -197,7 +197,7 @@ Review | Signoff date | Not Started | [PRE_VERIFIED_SUB_MODULES_V2]: {{}} [V3_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V3 +### V3 Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------|-------------|------------------ diff --git a/hw/ip/alert_handler/doc/dv_plan/index.md b/hw/ip/alert_handler/doc/dv_plan/index.md index b0b59cffa001f..d063539941ff7 100644 --- a/hw/ip/alert_handler/doc/dv_plan/index.md +++ b/hw/ip/alert_handler/doc/dv_plan/index.md @@ -12,7 +12,7 @@ title: "ALERT_HANDLER DV Plan" * Partially verify ping_timer ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/alert_handler/dv/latest/results.html) diff --git a/hw/ip/entropy_src/data/entropy_src.prj.hjson b/hw/ip/entropy_src/data/entropy_src.prj.hjson index a5ea0fc6ac681..f0f1d25b0e71d 100644 --- a/hw/ip/entropy_src/data/entropy_src.prj.hjson +++ b/hw/ip/entropy_src/data/entropy_src.prj.hjson @@ -4,6 +4,8 @@ { name: "entropy_src", + design_spec: "hw/ip/entropy_src/doc", + checklist: "hw/ip/entropy_src/doc/checklist", version: "0.5", life_stage: "L0", } diff --git a/hw/ip/flash_ctrl/data/flash_ctrl.prj.hjson b/hw/ip/flash_ctrl/data/flash_ctrl.prj.hjson index 587fbe0fbdc2c..2ecb6b392af6c 100644 --- a/hw/ip/flash_ctrl/data/flash_ctrl.prj.hjson +++ b/hw/ip/flash_ctrl/data/flash_ctrl.prj.hjson @@ -4,6 +4,8 @@ { name: "flash_ctrl", + design_spec: "hw/ip/flash_ctrl/doc", + checklist: "hw/ip/flash_ctrl/doc/checklist", version: "0.5", life_stage: "L1", design_stage: "D1", diff --git a/hw/ip/gpio/data/gpio.prj.hjson b/hw/ip/gpio/data/gpio.prj.hjson index 7a45ea56573fe..5e74c5b80e7ba 100644 --- a/hw/ip/gpio/data/gpio.prj.hjson +++ b/hw/ip/gpio/data/gpio.prj.hjson @@ -4,6 +4,9 @@ { name: "gpio", + design_spec: "hw/ip/gpio/doc", + dv_plan: "hw/ip/gpio/doc/dv_plan", + checklist: "hw/ip/gpio/doc/checklist", revisions: [ { version: "1.0", @@ -18,7 +21,6 @@ life_stage: "L1", design_stage: "D2", verification_stage: "V2", - commit_id: "f3039d7006ca8ebd45ae0b52b22864983876175d", notes: "Rolled back to D2 as the register module is updated", } ] diff --git a/hw/ip/gpio/doc/dv_plan/index.md b/hw/ip/gpio/doc/dv_plan/index.md index 61daf744a139e..5486ae86a385e 100644 --- a/hw/ip/gpio/doc/dv_plan/index.md +++ b/hw/ip/gpio/doc/dv_plan/index.md @@ -10,7 +10,7 @@ title: "GPIO DV Plan" * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/gpio/dv/latest/results.html) diff --git a/hw/ip/hmac/data/hmac.prj.hjson b/hw/ip/hmac/data/hmac.prj.hjson index e52c896b5b3dc..6e2f87f9362df 100644 --- a/hw/ip/hmac/data/hmac.prj.hjson +++ b/hw/ip/hmac/data/hmac.prj.hjson @@ -4,6 +4,9 @@ { name: "hmac", + design_spec: "hw/ip/hmac/doc", + dv_plan: "hw/ip/hmac/doc/dv_plan", + checklist: "hw/ip/hmac/doc/checklist", revisions: [ { version: "0.5", @@ -18,7 +21,6 @@ life_stage: "L1", design_stage: "D2", verification_stage: "V1", - commit_id: "48fd7fd2d27c844acf909cfd7dc2b86f0f4e8e43", notes: "Rolled back to D2 in order to add the first alert", } ] diff --git a/hw/ip/hmac/doc/dv_plan/index.md b/hw/ip/hmac/doc/dv_plan/index.md index accb1b4bec43b..371452aa4cbdc 100644 --- a/hw/ip/hmac/doc/dv_plan/index.md +++ b/hw/ip/hmac/doc/dv_plan/index.md @@ -10,7 +10,7 @@ title: "HMAC DV Plan" * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/hmac/dv/latest/results.html) diff --git a/hw/ip/i2c/data/i2c.prj.hjson b/hw/ip/i2c/data/i2c.prj.hjson index b370b06d455ea..d7ebfbccd8a72 100644 --- a/hw/ip/i2c/data/i2c.prj.hjson +++ b/hw/ip/i2c/data/i2c.prj.hjson @@ -4,6 +4,8 @@ { name: "i2c", + design_spec: "hw/ip/i2c/doc", + dv_plan: "hw/ip/i2c/doc/dv_plan", version: "0.5", life_stage: "L1", design_stage: "D0", diff --git a/hw/ip/i2c/doc/dv_plan/index.md b/hw/ip/i2c/doc/dv_plan/index.md index 95ab2820349b2..217ca7b3f6e8c 100644 --- a/hw/ip/i2c/doc/dv_plan/index.md +++ b/hw/ip/i2c/doc/dv_plan/index.md @@ -10,7 +10,7 @@ title: "I2C DV Plan" * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/i2c/dv/latest/results.html) diff --git a/hw/ip/nmi_gen/data/nmi_gen.prj.hjson b/hw/ip/nmi_gen/data/nmi_gen.prj.hjson index 53ddfc3bec670..9eff44c0b6250 100644 --- a/hw/ip/nmi_gen/data/nmi_gen.prj.hjson +++ b/hw/ip/nmi_gen/data/nmi_gen.prj.hjson @@ -4,6 +4,7 @@ { name: "nmi_gen", + design_spec: "hw/ip/nmi_gen/doc", version: "0.5", life_stage: "L1", design_stage: "D0", diff --git a/hw/ip/padctrl/data/padctrl.prj.hjson b/hw/ip/padctrl/data/padctrl.prj.hjson index 549dcb8854cd0..ca2a5dc51a1b8 100644 --- a/hw/ip/padctrl/data/padctrl.prj.hjson +++ b/hw/ip/padctrl/data/padctrl.prj.hjson @@ -4,6 +4,8 @@ { name: "padctrl", + design_spec: "hw/ip/padctrl/doc", + checklist: "hw/ip/padctrl/doc/checklist", version: "0.5", life_stage: "L1", design_stage: "D1", diff --git a/hw/ip/padctrl/doc/checklist.md b/hw/ip/padctrl/doc/checklist.md index f4fb8dc00f4c9..25685005d8d2b 100644 --- a/hw/ip/padctrl/doc/checklist.md +++ b/hw/ip/padctrl/doc/checklist.md @@ -103,7 +103,7 @@ Review | Signoff date | Not Started | ## Verification Checklist -### Checklists for milestone V1 +### V1 Type | Item | Resolution | Note/Collaterals --------------|---------------------------------------|-------------|------------------ @@ -146,7 +146,7 @@ Review | Signoff date | Not Started | [STD_TEST_CATEGORIES_PLANNED]: {{}} [V2_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V2 +### V2 Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------------|-------------|------------------ @@ -183,7 +183,7 @@ Review | Signoff date | Not Started | [PRE_VERIFIED_SUB_MODULES_V2]: {{}} [V3_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V3 +### V3 Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------|-------------|------------------ diff --git a/hw/ip/pinmux/data/pinmux.prj.hjson b/hw/ip/pinmux/data/pinmux.prj.hjson index b753e6ec7f6b9..0c2b47b0c9a5b 100644 --- a/hw/ip/pinmux/data/pinmux.prj.hjson +++ b/hw/ip/pinmux/data/pinmux.prj.hjson @@ -4,6 +4,8 @@ { name: "pinmux", + design_spec: "hw/ip/pinmux/doc", + checklist: "hw/ip/pinmux/doc/checklist", version: "0.5", life_stage: "L1", design_stage: "D1", diff --git a/hw/ip/pinmux/doc/checklist.md b/hw/ip/pinmux/doc/checklist.md index eae1803c078a0..bb9fa2b0c4f70 100644 --- a/hw/ip/pinmux/doc/checklist.md +++ b/hw/ip/pinmux/doc/checklist.md @@ -103,7 +103,7 @@ Review | Signoff date | Not Started | ## Verification Checklist -### Checklists for milestone V1 +### V1 Type | Item | Resolution | Note/Collaterals --------------|---------------------------------------|-------------|------------------ @@ -146,7 +146,7 @@ Review | Signoff date | Not Started | [STD_TEST_CATEGORIES_PLANNED]: {{}} [V2_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V2 +### V2 Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------------|-------------|------------------ @@ -183,7 +183,7 @@ Review | Signoff date | Not Started | [PRE_VERIFIED_SUB_MODULES_V2]: {{}} [V3_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V3 +### V3 Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------|-------------|------------------ diff --git a/hw/ip/rv_core_ibex/data/rv_core_ibex.prj.hjson b/hw/ip/rv_core_ibex/data/rv_core_ibex.prj.hjson index 36ac2da2a9b7a..01605885c8b58 100644 --- a/hw/ip/rv_core_ibex/data/rv_core_ibex.prj.hjson +++ b/hw/ip/rv_core_ibex/data/rv_core_ibex.prj.hjson @@ -4,6 +4,8 @@ { name: "rv_core_ibex", + design_spec: "hw/ip/rv_core_ibex/doc", + checklist: "hw/ip/rv_core_ibex/doc/checklist", version: "0.5", life_stage: "L1", design_stage: "D2", diff --git a/hw/ip/rv_core_ibex/doc/checklist.md b/hw/ip/rv_core_ibex/doc/checklist.md index fdbcfee7a290d..8a612fc82d893 100644 --- a/hw/ip/rv_core_ibex/doc/checklist.md +++ b/hw/ip/rv_core_ibex/doc/checklist.md @@ -104,7 +104,7 @@ Review | [REVIEW_SW_ERRATA][] | Not Started | ## Verification Checklist -### Checklists for milestone V1 +### V1 Type | Item | Resolution | Note/Collaterals --------------|---------------------------------------|-------------|------------------ Documentation | [DV_PLAN_DRAFT_COMPLETED][] | Waived | Plan created, but does not conform to other templates @@ -146,7 +146,7 @@ Review | [V2_CHECKLIST_SCOPED][] | Done | [STD_TEST_CATEGORIES_PLANNED]: {{}} [V2_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V2 +### V2 Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------------|-------------|------------------ Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | Not Started | @@ -180,7 +180,7 @@ Review | [V3_CHECKLIST_SCOPED][] | Not Started | [PRE_VERIFIED_SUB_MODULES_V2]: {{}} [V3_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V3 +### V3 Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------|-------------|------------------ Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | Not Started | diff --git a/hw/ip/rv_dm/data/rv_dm.prj.hjson b/hw/ip/rv_dm/data/rv_dm.prj.hjson index 64c1050f9c82b..72f5b307ccc35 100644 --- a/hw/ip/rv_dm/data/rv_dm.prj.hjson +++ b/hw/ip/rv_dm/data/rv_dm.prj.hjson @@ -4,6 +4,7 @@ { name: "rv_dm", + design_spec: "hw/ip/rv_dm/doc", version: "0.5", life_stage: "L1", design_stage: "D0", diff --git a/hw/ip/rv_plic/data/rv_plic.prj.hjson b/hw/ip/rv_plic/data/rv_plic.prj.hjson index e61a232ee886f..df7d425195d5c 100644 --- a/hw/ip/rv_plic/data/rv_plic.prj.hjson +++ b/hw/ip/rv_plic/data/rv_plic.prj.hjson @@ -4,6 +4,7 @@ { name: "rv_plic", + design_spec: "hw/ip/rv_plic/doc", version: "0.5", life_stage: "L1", design_stage: "D0", diff --git a/hw/ip/rv_plic/doc/dv_plan/index.md b/hw/ip/rv_plic/doc/dv_plan/index.md index 7f8199816bc12..eaf3998039500 100644 --- a/hw/ip/rv_plic/doc/dv_plan/index.md +++ b/hw/ip/rv_plic/doc/dv_plan/index.md @@ -12,7 +12,7 @@ title: "RV_PLIC DV Plan" * Verify TileLink device protocol compliance with a FPV based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * FPV dashboard (link TBD) diff --git a/hw/ip/rv_timer/data/rv_timer.prj.hjson b/hw/ip/rv_timer/data/rv_timer.prj.hjson index 534f147a53f7d..6fcc391438f2d 100644 --- a/hw/ip/rv_timer/data/rv_timer.prj.hjson +++ b/hw/ip/rv_timer/data/rv_timer.prj.hjson @@ -4,6 +4,9 @@ { name: "rv_timer", + design_spec: "hw/ip/rv_timer/doc", + dv_plan: "hw/ip/rv_timer/doc/dv_plan", + checklist: "hw/ip/rv_timer/doc/checklist", revisions: [ { version: "0.5", @@ -18,7 +21,6 @@ life_stage: "L1", design_stage: "D2", verification_stage: "V2", - commit_id: "f3039d7006ca8ebd45ae0b52b22864983876175d", notes: "Rolled back to D2 as the register module is updated", } ] diff --git a/hw/ip/rv_timer/doc/dv_plan/index.md b/hw/ip/rv_timer/doc/dv_plan/index.md index 03bdb19c5b4cc..ab74282f889aa 100644 --- a/hw/ip/rv_timer/doc/dv_plan/index.md +++ b/hw/ip/rv_timer/doc/dv_plan/index.md @@ -10,7 +10,7 @@ title: "RV_TIMER DV Plan" * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/rv_timer/dv/latest/results.html) diff --git a/hw/ip/spi_device/data/spi_device.prj.hjson b/hw/ip/spi_device/data/spi_device.prj.hjson index 3b2281c0dc740..49a9994d7fb3e 100644 --- a/hw/ip/spi_device/data/spi_device.prj.hjson +++ b/hw/ip/spi_device/data/spi_device.prj.hjson @@ -4,6 +4,9 @@ { name: "spi_device", + design_spec: "hw/ip/spi_device/doc", + dv_plan: "hw/ip/spi_device/doc/dv_plan", + checklist: "hw/ip/spi_device/doc/checklist", revisions: [ { version: "0.5", diff --git a/hw/ip/spi_device/doc/dv_plan/index.md b/hw/ip/spi_device/doc/dv_plan/index.md index bdc7320e7602e..54ddfb568b973 100644 --- a/hw/ip/spi_device/doc/dv_plan/index.md +++ b/hw/ip/spi_device/doc/dv_plan/index.md @@ -11,7 +11,7 @@ title: "SPI Device DV Plan" * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/spi_device/dv/latest/results.html) diff --git a/hw/ip/tlul/data/tlul.prj.hjson b/hw/ip/tlul/data/tlul.prj.hjson index 89ccab1371766..a3c47ab2a6284 100644 --- a/hw/ip/tlul/data/tlul.prj.hjson +++ b/hw/ip/tlul/data/tlul.prj.hjson @@ -4,6 +4,9 @@ { name: "tlul", + design_spec: "hw/ip/tlul/doc", + dv_plan: "hw/ip/tlul/doc/dv_plan", + checklist: "hw/top_earlgrey/ip/xbar/doc/checklist", revisions: [ { version: "0.5", @@ -18,8 +21,7 @@ life_stage: "L1", design_stage: "D1", verification_stage: "V1", - commit_id: "2366287ed15fd02c09f05ce61c5d9ef2ae280181", - notes: "Rolled back to D1V1 as more features (like multi-clock) are being updated" + notes: "" } ] } diff --git a/hw/ip/tlul/doc/dv_plan/index.md b/hw/ip/tlul/doc/dv_plan/index.md index d2241a63d8b76..b5fa640a3d26d 100644 --- a/hw/ip/tlul/doc/dv_plan/index.md +++ b/hw/ip/tlul/doc/dv_plan/index.md @@ -11,7 +11,7 @@ title: "TLUL XBAR DV Plan" * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages" >}}) * DV regression results dashboard (link TBD) diff --git a/hw/ip/uart/data/uart.prj.hjson b/hw/ip/uart/data/uart.prj.hjson index bf8b7bc50084d..ad3976f9fd74a 100644 --- a/hw/ip/uart/data/uart.prj.hjson +++ b/hw/ip/uart/data/uart.prj.hjson @@ -4,6 +4,9 @@ { name: "uart", + design_spec: "hw/ip/uart/doc", + dv_plan: "hw/ip/uart/doc/dv_plan", + checklist: "hw/ip/uart/doc/checklist", revisions: [ { version: "1.0", @@ -18,8 +21,7 @@ life_stage: "L1", design_stage: "D2", verification_stage: "V2", - commit_id: "f3039d7006ca8ebd45ae0b52b22864983876175d", - notes: "Rolled back to D2 as the register module is updated", + notes: "Rolled back to D2 as the register module is updated" } ] } diff --git a/hw/ip/uart/doc/checklist.md b/hw/ip/uart/doc/checklist.md index 799fe4fee345b..e450d7825489a 100644 --- a/hw/ip/uart/doc/checklist.md +++ b/hw/ip/uart/doc/checklist.md @@ -110,7 +110,8 @@ Review | Signoff date | Done | 2019-10-31 ## Verification Checklist -### Checklists for milestone V1 +### V1 + Type | Item | Resolution | Note/Collaterals --------------|---------------------------------------|-------------|------------------ Documentation | [DV_PLAN_DRAFT_COMPLETED][] | Done | [uart_dv_plan]({{}}) @@ -159,7 +160,8 @@ Review | Signoff date | Done | 2019-10-28 [STD_TEST_CATEGORIES_PLANNED]: {{}} [V2_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V2 +### V2 + Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------------|-------------|------------------ Documentation | [DESIGN_DELTAS_CAPTURED_V2][] | N/A | @@ -202,7 +204,8 @@ Review | Signoff date | Done | 2019-10- [PRE_VERIFIED_SUB_MODULES_V2]: {{}} [V3_CHECKLIST_SCOPED]: {{}} -### Checklists for milestone V3 +### V3 + Type | Item | Resolution | Note/Collaterals --------------|-----------------------------------|-------------|------------------ Documentation | [DESIGN_DELTAS_CAPTURED_V3][] | N/A | diff --git a/hw/ip/uart/doc/dv_plan/index.md b/hw/ip/uart/doc/dv_plan/index.md index dafa64b37da78..98b41d2fd9fc4 100644 --- a/hw/ip/uart/doc/dv_plan/index.md +++ b/hw/ip/uart/doc/dv_plan/index.md @@ -11,7 +11,7 @@ title: "UART DV Plan" * Verify TileLink device protocol compliance with an SVA based testbench ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/uart/dv/latest/results.html) diff --git a/hw/ip/usbdev/data/usbdev.prj.hjson b/hw/ip/usbdev/data/usbdev.prj.hjson index 1c5a0661153ed..e3a68d5842712 100644 --- a/hw/ip/usbdev/data/usbdev.prj.hjson +++ b/hw/ip/usbdev/data/usbdev.prj.hjson @@ -4,6 +4,8 @@ { name: "usbdev", + design_spec: "hw/ip/usbdev/doc", + dv_plan: "hw/ip/usbdev/doc/dv_plan", version: "0.5", life_stage: "L1", design_stage: "D0", diff --git a/hw/ip/usbdev/doc/dv_plan/index.md b/hw/ip/usbdev/doc/dv_plan/index.md index 731e215f4e7e9..dcd322cd1d35b 100644 --- a/hw/ip/usbdev/doc/dv_plan/index.md +++ b/hw/ip/usbdev/doc/dv_plan/index.md @@ -12,7 +12,7 @@ title: "USBDEV DV Plan" * Verify TileLink device protocol compliance with an SVA based testbench. ## Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/usbdev/dv/latest/results.html) diff --git a/site/docs/layouts/shortcodes/dashboard.html b/site/docs/layouts/shortcodes/dashboard.html index 92d637ad6db01..e3ff1c01763b7 100644 --- a/site/docs/layouts/shortcodes/dashboard.html +++ b/site/docs/layouts/shortcodes/dashboard.html @@ -1,16 +1,17 @@ - - - - - - - - - - - - + + + + + + + + + + + {{ readFile (path.Join .Site.Params.generatedRoot (.Get 0) "dashboard") | safeHTML }} - +
ModuleVersionLife StageDesign StageVerification StageCommit IDNotes
Design SpecDV PlanVersionDevelopment StageNotes
diff --git a/util/dashboard/dashboard_validate.py b/util/dashboard/dashboard_validate.py index dd1a05d3524c5..f8326eebeb48b 100644 --- a/util/dashboard/dashboard_validate.py +++ b/util/dashboard/dashboard_validate.py @@ -33,6 +33,10 @@ def check_keys(obj, required_keys, optional_keys, err_prefix): 'life_stage': ['s', "life stage of module"] } field_optional = { + 'design_spec': + ['s', "path to the design specification, relative to repo root"], + 'dv_plan': ['s', "path to the DV plan, relative to repo root"], + 'checklist': ['s', "path to the checklist, relative to repo root"], 'design_stage': ['s', "design stage of module"], 'verification_stage': ['s', "verification stage of module"], 'notes': ['s', "random notes"], diff --git a/util/dashboard/gen_dashboard_entry.py b/util/dashboard/gen_dashboard_entry.py index 0a293ba7d3170..badb172d08328 100644 --- a/util/dashboard/gen_dashboard_entry.py +++ b/util/dashboard/gen_dashboard_entry.py @@ -5,15 +5,17 @@ Generate HTML documentation from validated dashboard Hjson tree """ -import sys -import hjson import html -import re -import dashboard.dashboard_validate as dashboard_validate import logging as log import os.path +import re +import sys + +import hjson import mistletoe as mk +import dashboard.dashboard_validate as dashboard_validate + def genout(outfile, msg): outfile.write(msg) @@ -33,11 +35,107 @@ def genout(outfile, msg): 'V3': 'Verification Complete' } +# TODO: This is relative to the dashboard, which is currently located at +# hw/_index.md. +docs_server = "../.." + def convert_stage(stagestr): return STAGE_STRINGS.get(stagestr, "UNKNOWN") +# Link module name with its design spec doc. +def get_linked_design_spec(obj): + result = "" + if 'design_spec' in obj.keys(): + url = docs_server + "/" + html.escape(obj['design_spec']) + result = "".format(url) + result += "{}".format(html.escape(obj['name'])) + else: + result = html.escape(obj['name']) + + return result + + +# Provide the link to the DV plan. +def get_linked_dv_plan(obj): + if 'dv_plan' in obj.keys(): + url = docs_server + "/" + html.escape(obj['dv_plan']) + return "DV".format(url) + else: + return "" + + +# Link D/V stages with the checklist table. +def get_linked_checklist(obj, rev, stage, is_latest_rev=True): + if not stage or stage not in rev: return "" + + url = "" + in_page_ref = "" + if rev[stage] not in ["D0", "V0"]: + # if in D0 or V0 stage, there is no in-page reference. + in_page_ref = "#{}".format(html.escape(rev[stage]).lower()) + + # If the checklist is available, the commit id is available, and it is not + # the latest revision, link to the committed version of the checklist. + # Else, if checklist is available, then link to the current version of the + # checklist html. + # Else, link to the template. + if 'checklist' in obj and 'commit_id' in rev and not is_latest_rev: + url = "https://github.com/lowrisc/opentitan/blob/{}/{}.md{}".format( + rev['commit_id'], obj['checklist'], in_page_ref) + elif 'checklist' in obj: + url = "{}/{}{}".format(docs_server, html.escape(obj['checklist']), + in_page_ref) + else: + # There is no checklist available, so point to the template. + url = "https://github.com/lowrisc/opentitan/blob/master/" + url += "doc/project/ip_checklist.md.tpl" + + return "{}".format(url, html.escape(rev[stage])) + + +# Link development stages in "L# : D# : V#" format. +# Hover text over each L, D, V indicates the stage mapping. +# D and V stages link to actual checklist items. +def get_development_stage(obj, rev, is_latest_rev=True): + if "life_stage" not in rev: return " " + + life_stage = rev['life_stage'] + life_stage_mapping = convert_stage(life_stage) + separator = " : " + + if life_stage != 'L0' and 'design_stage' in rev: + design_stage = rev['design_stage'] + design_stage_mapping = convert_stage(design_stage) + else: + design_stage = None + + if life_stage != 'L0' and 'verification_stage' in rev: + verification_stage = rev['verification_stage'] + verification_stage_mapping = convert_stage(verification_stage) + else: + verification_stage = None + + result = "{}".format( + html.escape(life_stage_mapping), html.escape(life_stage)) + + if design_stage: + result += separator + result += "{}".format( + html.escape(design_stage_mapping), + get_linked_checklist(obj, rev, 'design_stage', is_latest_rev)) + + if verification_stage: + result += separator + result += "{}".format( + html.escape(verification_stage_mapping), + get_linked_checklist(obj, rev, 'verification_stage', + is_latest_rev)) + + return result + + # Create dashboard of hardware IP development status def gen_dashboard_html(hjson_path, outfile): with hjson_path: @@ -67,34 +165,15 @@ def print_version1_format(obj, outfile): # yapf: disable genout(outfile, " \n") + name = html.escape(obj['name']) genout(outfile, " " + - html.escape(obj['name']) + "\n") + get_linked_design_spec(obj) + "\n") + genout(outfile, " " + + get_linked_dv_plan(obj) + "\n") genout(outfile, " " + html.escape(obj['version']) + "\n") - genout(outfile, " " + - html.escape(life_stage) + "\n") - if life_stage != 'L0' and 'design_stage' in obj: - design_stage_mapping = convert_stage(obj['design_stage']) - genout(outfile, - " " + - html.escape(obj['design_stage']) + "\n") - else: - genout(outfile, - "  \n") - if life_stage != 'L0' and 'verification_stage' in obj: - verification_stage_mapping = convert_stage(obj['verification_stage']) - genout(outfile, - " " + - html.escape(obj['verification_stage']) + "\n") - else: - genout(outfile, - "  \n") - - # Empty commit ID - genout(outfile, "  \n") + genout(outfile, " " + + get_development_stage(obj, obj) + "\n") if 'notes' in obj: genout(outfile, @@ -110,6 +189,7 @@ def print_multiversion_format(obj, outfile): # Sort the revision list based on the version field. # TODO: If minor version goes up gte than 10? revisions = sorted(obj["revisions"], key=lambda x: x["version"]) + latest_rev = len(revisions) - 1 outstr = "" for i, rev in enumerate(revisions): outstr += " \n" @@ -117,50 +197,28 @@ def print_multiversion_format(obj, outfile): # If only one entry in `revisions`, no need of `rowspan`. if len(revisions) == 1: outstr += " " - outstr += html.escape(obj['name']) + "\n" + outstr += get_linked_design_spec(obj) + "\n" + outstr += " " + outstr += get_linked_dv_plan(obj) + "\n" # Print out the module name in the first entry only elif i == 0: outstr += " ".format( len(revisions)) - outstr += html.escape(obj['name']) + "\n" + outstr += get_linked_design_spec(obj) + "\n" + outstr += " ".format( + len(revisions)) + outstr += get_linked_dv_plan(obj) + "\n" # Version outstr += " " outstr += html.escape(rev['version']) + "\n" - # Life Stage - life_stage = rev['life_stage'] - life_stage_mapping = convert_stage(rev['life_stage']) - - outstr += " " - outstr += html.escape(life_stage) + "\n" - - if life_stage != 'L0' and 'design_stage' in rev: - design_stage_mapping = convert_stage(rev['design_stage']) - outstr += " " - outstr += html.escape(rev['design_stage']) + "\n" - else: - outstr += "  \n" - - if life_stage != 'L0' and 'verification_stage' in rev: - verification_stage_mapping = convert_stage( - rev['verification_stage']) - outstr += " " - outstr += html.escape(rev['verification_stage']) + "\n" - else: - outstr += "  \n" - - if 'commit_id' in rev: - outstr += " " - outstr += "{}".format( - rev['commit_id'], rev['commit_id'][0:7]) - outstr += "\n" - else: - outstr += "  \n" + # Development Stage + outstr += " " + outstr += get_development_stage(obj, rev, (i == latest_rev)) + outstr += "\n" + # Notes if 'notes' in rev and rev['notes'] != '': outstr += " " + mk.markdown( rev['notes']).rstrip() + "\n" diff --git a/util/uvmdvgen/dv_plan.md.tpl b/util/uvmdvgen/dv_plan.md.tpl index 3cab56e357aa7..75bbee2254718 100644 --- a/util/uvmdvgen/dv_plan.md.tpl +++ b/util/uvmdvgen/dv_plan.md.tpl @@ -19,7 +19,7 @@ ${'##'} Goals * Verify TileLink device protocol compliance with an SVA based testbench ${'##'} Current status -* [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) +* [Design & verification stage]({{< relref "hw" >}}) * [HW development stages]({{< relref "doc/project/hw_stages" >}}) * [Simulation results](https://reports.opentitan.org/hw/ip/${name}/dv/latest/results.html)