From 8573fa2a303fd0651e5e2b395de538297a007152 Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Fri, 1 Nov 2019 14:49:56 -0700 Subject: [PATCH] [doc] clean up product, project documentation --- _index.md | 24 ++-- doc/product.md | 25 ---- doc/project.md | 47 -------- doc/project/_index.md | 18 +++ doc/{rm => project}/checklist.md | 2 +- doc/project/hw_dashboard.md | 2 +- doc/{ug => project}/hw_stages.md | 14 +-- doc/project/ip_checklist.md.tpl | 170 ++++++++++++++-------------- doc/rm/_index.md | 1 - doc/rm/c_cpp_coding_style.md | 2 + doc/ug/_index.md | 7 +- doc/ug/design.md | 12 +- doc/ug/dv_methodology.md | 2 +- doc/ug/getting_started_design.md | 6 +- hw/dv/doc/dv_plan_template.md | 2 +- hw/ip/gpio/doc/dv_plan/index.md | 2 +- hw/ip/hmac/doc/dv_plan/index.md | 2 +- hw/ip/i2c/doc/dv_plan/index.md | 2 +- hw/ip/rv_timer/doc/checklist.md | 168 +++++++++++++-------------- hw/ip/rv_timer/doc/dv_plan/index.md | 2 +- hw/ip/uart/doc/checklist.md | 162 +++++++++++++------------- hw/ip/uart/doc/dv_plan/index.md | 2 +- util/testplanner/README.md | 2 +- util/uvmdvgen/dv_plan.md.tpl | 2 +- 24 files changed, 308 insertions(+), 370 deletions(-) delete mode 100644 doc/product.md delete mode 100644 doc/project.md create mode 100644 doc/project/_index.md rename doc/{rm => project}/checklist.md (98%) rename doc/{ug => project}/hw_stages.md (95%) diff --git a/_index.md b/_index.md index 4b10d0828fc4b..9f0601d86d95e 100644 --- a/_index.md +++ b/_index.md @@ -1,10 +1,8 @@ # Introduction to OpenTitan -The OpenTitan project aims to design and ship an open source, industry-leading piece of secure silicon for Root of Trust applications. -OpenTitan is administered by lowRISC CIC as a collaborative -[project]({{< relref "doc/project.md" >}}) -to produce high quality, open IP for instantiation as a full-featured -[product]({{< relref "doc/product.md" >}}). +[OpenTitan](https://opentitan.org) is an open source silicon Root of Trust (RoT) project. +OpenTitan will make the silicon RoT design and implementation more transparent, trustworthy, and secure for enterprises, platform providers, and chip manufacturers. +OpenTitan is administered by lowRISC CIC as a collaborative [project]({{< relref "doc/project" >}}) to produce high quality, open IP for instantiation as a full-featured product. This repository exists to enable collaboration across partners participating in the OpenTitan project. To get started using or contributing to the OpenTitan codebase, see the @@ -13,6 +11,7 @@ For details on coding styles or how to use our project-specific tooling, see the [reference manuals]({{< relref "doc/rm" >}}). [This page]({{< relref "hw" >}}) contains technical documentation on the SoC, the Ibex processor core, and the individual IP blocks. +For questions about how the project is organized, see the [project]({{< relref "doc/project" >}}) landing spot for more information. ## Repository Structure @@ -24,28 +23,21 @@ See also [repository readme]({{< relref "README.md" >}}) for licensing informati ## Documentation Sections -* [Project]({{< relref "doc/project.md" >}}) +* [Project]({{< relref "doc/project" >}}) * How the OpenTitan project is organized - * Governance of the program, how to get involved * Progress tracking -* [Product]({{< relref "doc/product.md" >}}) - * What is the OpenTitan product - * Architecture and technical hardware specifications - * Software roadmap - * Security and manufacturing * [User Guides]({{< relref "doc/ug" >}}) * How to get started with the repo * How to emulate on an FPGA + * How hardware design is done in OpenTitan * How verification is done in OpenTitan - * How validation is done on FPGA in the project * [Reference Manuals]({{< relref "doc/rm" >}}) * Defining comportable IP peripherals - * Coding style guides for Verilog, Python, and Markdown + * Coding style guides for Verilog, Python, Hjson, C/C++ and Markdown * OpenTitan tools - * Working with vendor tools * [Hardware Specifications]({{< relref "hw" >}}) * Top-level SoC * Ibex processor core * Comportable IP blocks * [Tools]({{< relref "util" >}}) - * Readme's of OpenTitan tools + * READMEs of OpenTitan tools diff --git a/doc/product.md b/doc/product.md deleted file mode 100644 index 4da82dc540168..0000000000000 --- a/doc/product.md +++ /dev/null @@ -1,25 +0,0 @@ -# The OpenTitan Product - -## Overview - -<Paragraph about how OpenTitan will be used as a product, reference to Titan, brief purpose, etc> - -## Features - -<Paragraph about the features of the silicon and system around it, how it is used, pointer to top level silicon technical specification ../hw/doc/top_earlgrey.md> - -## System Integration - -<Paragraph about integration concepts at a high level, admissible architectures, eventual goal of integration schematics, OTPF> - -## Open Source FPGA versus Final Silicon - -<Brief dissertation into the distinction between OpenTitan the Open Source project (mention of FPGA as a target) and OpenTitan the silicon incarnation. -Methods to ensure they are equivalent (early reference to compliance regime). -Distinctions of silicon needs (foundry collateral, analog designs, security hardening, ASIC signoff flow).> - -## Software and firmware - -<mention of the importance of the software and firmware deliveries. -List of expected software and firmware deliveries to come (Boot ROM, boot loaders, manufacturing code, operating system, final application, DIFs, etc).> - diff --git a/doc/project.md b/doc/project.md deleted file mode 100644 index 0fd99ea5f998f..0000000000000 --- a/doc/project.md +++ /dev/null @@ -1,47 +0,0 @@ -# Introduction to the OpenTitan Project - -<Deeper dive into what the project is all about, as compared to intro paragraph. -Open source strategy; History; Who are we?; Etc (more deep from the intro paragraph)> - -## OpenTitan project governance - -<Governance. -Keep the "garden" healthy; -Corp partners; -Technical 'code owners' etc; -How to get commit permission / acceptance; -How are PRs accepted; what is the process by which things are allowed / rejected; -partner criteria; -code of conduct; and maintaining code and community health; -Code style and format issues; -steering committees; -Trademark use policy; -License policy / CLA> - -## How to get involved - -<Just brief points as to how to start out; -"My company just signed up, how do I figure out what to work on and who to talk to?"; -link to getting started user guides; -Team drive (for internal/confidential docs) vs github, mailing list vs chat, etc.> - -## Quality standards for open hardware IP - -<Maturity standards - what they are; -Articulate maturity/quality level per IP (could vary across different IPs); -Different "support" expectation; -How we maintain quality; -possible reference to certification; -Process to ensure logical security of included IP; -Security exposure/disclosure.> - -## Project status - -<Process - who is doing what, current status, how to document; -List of partners; list of contributing individuals -Some presentation of current status; -Code coverage + completion; -Test coverage; -alpha/beta designation; -design dashboard.> - diff --git a/doc/project/_index.md b/doc/project/_index.md new file mode 100644 index 0000000000000..dbdaaae93036e --- /dev/null +++ b/doc/project/_index.md @@ -0,0 +1,18 @@ +--- +title: "Introduction to the OpenTitan Project" +--- + +OpenTitan is a collaborative hardware and software development program with contributors from many organization. +This area gives some more information about how the project itself is organized. +More information will be added over time. + +## Quality standards for open hardware IP + +In order to gauge the quality of the different IP that is in our repository, we define a series of [Hardware Development Stages]({{< relref "hw_stages" >}}) to track the designs. +The current status of different IP is reflected in the [HW Development Stages Dashboard]({{< relref "hw_dashboard" >}}). +The final state for developed IP is *Signed Off*, indicating that design and verification is complete, and the IP should be bug free. +To make it to that stage, a [Hardware Signoff Checklist]({{< relref "checklist.md" >}}) is used to confirm completion. + +## Initiating new development + +The [OpenTitan RFC process]({{< relref "rfc_process" >}}) guides developers on how to initiate new development within the program. diff --git a/doc/rm/checklist.md b/doc/project/checklist.md similarity index 98% rename from doc/rm/checklist.md rename to doc/project/checklist.md index 18a7cd271b129..e2336f014c843 100644 --- a/doc/rm/checklist.md +++ b/doc/project/checklist.md @@ -2,7 +2,7 @@ title: "Signoff Checklist" --- -This document explains the recommended checklist items to review when transitioning from one [Hardware Stage]({{}}) to another, for both design and verification stages. +This document explains the recommended checklist items to review when transitioning from one [Hardware Stage]({{}}) to another, for both design and verification stages. It is expected that the items in each stage (D1, V1, etc) are completed. ## D1 diff --git a/doc/project/hw_dashboard.md b/doc/project/hw_dashboard.md index 997226258a06b..ace3f6e9aac57 100644 --- a/doc/project/hw_dashboard.md +++ b/doc/project/hw_dashboard.md @@ -3,6 +3,6 @@ This dashboard gives the current status of [Comportable](/doc/rm/comportability_specification) designs within the OpenTitan project. -See the [Hardware Development Stages](/doc/ug/hw_stages) for description of the hardware stages and how they are determined. +See the [Hardware Development Stages]({{< relref "/doc/project/hw_stages.md" >}}) for description of the hardware stages and how they are determined. {{< dashboard "hw/ip" >}} diff --git a/doc/ug/hw_stages.md b/doc/project/hw_stages.md similarity index 95% rename from doc/ug/hw_stages.md rename to doc/project/hw_stages.md index 162a070c38ed1..961073e53b2ae 100644 --- a/doc/ug/hw_stages.md +++ b/doc/project/hw_stages.md @@ -6,7 +6,7 @@ This document describes development stages for hardware within the OpenTitan pro This includes design and verification stages meant to give a high-level view of the status of a design. OpenTitan being an open-source program aimed at a high quality silicon release, the intent is to find a balance between the rigor of a heavy tapeout process and the more fluid workings of an open source development. -This document also serves as a guide to the *hardware design dashboard* (TODO: link), which gives the status of all of the designs in the OpenTitan repository. +This document also serves as a guide to the [hardware design dashboard]({{< relref "doc/project/hw_dashboard" >}}), which gives the status of all of the designs in the OpenTitan repository. This document aims to mostly give a more defined structure to the process that is already followed. Proper versioning of RTL designs is a complex topic. @@ -20,7 +20,7 @@ At the moment, this is strictly limited to a hardware design, but could be expan Transitions between these stages are decided by the Technical Committee via the RFC process. The first life stage is **Specification**. -The proposed design is written up and submitted through the *RFC process* (TODO: link). +The proposed design is written up and submitted through the [RFC process]({{< relref "doc/project/rfc_process" >}}). Depending on the complexity of the design and the guidance of the Technical Committee, it is possible a single design might require multiple RFCs. For example, a first RFC for the rationale, feature list, and a rough overview; followed by a more detailed RFC to get approval for the draft technical specification. As part of the specification process, the design author might reach out for feedback from a smaller group of reviewers while formulating an RFC proposal. @@ -143,10 +143,9 @@ Transitions for Design and Verification stages are _self-nominated_ in the sense In this manner other reviewers can challenge the transition in the standard pull request review process. These transitions should be done in their own PR (i.e. not interspersed with other changes), and the PR summary and commit message should give any necessary detail on how the transition criteria have been met, as well as any other notes useful for a reviewer. -The content below shows a proposal for the project file that contains the stage information. -The final content, location, and name of that file will be updated in this space soon. (TODO) - -`file: gpio.prj.hjson` +The content below shows the format of the project file that contains the stage information. +The file for a design named `name` should be placed under `hw/ip/name/data/name.prj.hjson`. +For example, `file: gpio.prj.hjson`: ```hjson { @@ -155,6 +154,7 @@ The final content, location, and name of that file will be updated in this space life_stage: "L1", design_stage: "D2", verification_stage: "V1", + notes: "information shown on the dashboard" } ``` @@ -185,4 +185,4 @@ This would require a new RFC process, and thus the Life Stage would start again The stages are reported externally via a script-generated table exposed on the external website. This status will be a summary of all `prj.hjson` files of all designs in the system. -The link to that table is here (TODO: link). +The link to that table is [here]({{< relref "doc/project/hw_dashboard" >}}). diff --git a/doc/project/ip_checklist.md.tpl b/doc/project/ip_checklist.md.tpl index 6cd9a53faf5bd..a8cdfd779f539 100644 --- a/doc/project/ip_checklist.md.tpl +++ b/doc/project/ip_checklist.md.tpl @@ -2,8 +2,8 @@ title: "${name.upper()} Checklist" --- -This checklist is for [Hardware Stage]({{< relref "/doc/ug/hw_stages.md" >}}) transitions for the [${name.upper()} peripheral.]({{< relref "index.md" >}}) -All checklist items refer to the content in the [Checklist.]({{< relref "/doc/rm/checklist.md" >}}) +This checklist is for [Hardware Stage]({{< relref "/doc/project/hw_stages.md" >}}) transitions for the [${name.upper()} peripheral.]({{< relref "index.md" >}}) +All checklist items refer to the content in the [Checklist.]({{< relref "/doc/project/checklist.md" >}}) ## Design Checklist @@ -24,22 +24,22 @@ Review | Reviewer(s) | Not Started | Review | Signoff date | Not Started | -[SPEC_COMPLETE]: {{}} -[CSR_DEFINED]: {{}} -[CLKRST_CONNECTED]: {{}} -[IP_TOP]: {{}} -[IP_INSTANCED]: {{}} -[MEM_INSTANCED_80]: {{}} -[FUNC_IMPLEMENTED]: {{}} -[ASSERT_KNOWN_ADDED]: {{}} -[LINT_SETUP]: {{}} -[D1_REVIEWED]: {{}} +[SPEC_COMPLETE]: {{}} +[CSR_DEFINED]: {{}} +[CLKRST_CONNECTED]: {{}} +[IP_TOP]: {{}} +[IP_INSTANCED]: {{}} +[MEM_INSTANCED_80]: {{}} +[FUNC_IMPLEMENTED]: {{}} +[ASSERT_KNOWN_ADDED]: {{}} +[LINT_SETUP]: {{}} +[D1_REVIEWED]: {{}} ### D2 Type | Item | Resolution | Note/Collaterals --------------|-------------------------|-------------|------------------ -Documentation | [NEW_FEATURES][] | Not Started | +Documentation | [NEW_FEATURES][] | Not Started | Documentation | [BLOCK_DIAGRAM][] | Not Started | Documentation | [DOC_INTERFACE][] | Not Started | Documentation | [MISSING_FUNC][] | Not Started | @@ -57,24 +57,24 @@ Code Quality | [CDC_SYNCMACRO][] | Not Started | Review | Reviewer(s) | Not Started | Review | Signoff date | Not Started | -[NEW_FEATURES]: {{}} -[BLOCK_DIAGRAM]: {{}} -[DOC_INTERFACE]: {{}} -[MISSING_FUNC]: {{}} -[FEATURE_FROZEN]: {{}} -[FEATURE_COMPLETE]: {{}} -[AREA_SANITY_CHECK]: {{}} -[DEBUG_BUS]: {{}} -[PORT_FROZEN]: {{}} -[ARCHITECTURE_FROZEN]: {{}} -[REVIEW_TODO]: {{}} -[STYLE_X]: {{}} -[STYLE_LINT_SETUP]: {{}} -[LINT_PASS]: {{}} -[CDC_SETUP]: {{}} -[CDC_SYNCMACRO]: {{}} -[FPGA_TIMING]: {{}} -[D2_REVIEWED]: {{}} +[NEW_FEATURES]: {{}} +[BLOCK_DIAGRAM]: {{}} +[DOC_INTERFACE]: {{}} +[MISSING_FUNC]: {{}} +[FEATURE_FROZEN]: {{}} +[FEATURE_COMPLETE]: {{}} +[AREA_SANITY_CHECK]: {{}} +[DEBUG_BUS]: {{}} +[PORT_FROZEN]: {{}} +[ARCHITECTURE_FROZEN]: {{}} +[REVIEW_TODO]: {{}} +[STYLE_X]: {{}} +[STYLE_LINT_SETUP]: {{}} +[LINT_PASS]: {{}} +[CDC_SETUP]: {{}} +[CDC_SYNCMACRO]: {{}} +[FPGA_TIMING]: {{}} +[D2_REVIEWED]: {{}} ### D3 @@ -93,18 +93,18 @@ Review | [REVIEW_SW_ERRATA][] | Not Started | Review | Reviewer(s) | Not Started | Review | Signoff date | Not Started | -[NEW_FEATURES_D3]: {{}} -[TODO_COMPLETE]: {{}} -[LINT_COMPLETE]: {{}} -[CDC_COMPLETE]: {{}} -[REVIEW_RTL]: {{}} -[REVIEW_DBG]: {{}} -[REVIEW_DELETED_FF]: {{}} -[REVIEW_SW_CSR]: {{}} -[REVIEW_SW_FATAL_ERR]: {{}} -[REVIEW_SW_CHANGE]: {{}} -[REVIEW_SW_ERRATA]: {{}} -[D3_REVIEWED]: {{}} +[NEW_FEATURES_D3]: {{}} +[TODO_COMPLETE]: {{}} +[LINT_COMPLETE]: {{}} +[CDC_COMPLETE]: {{}} +[REVIEW_RTL]: {{}} +[REVIEW_DBG]: {{}} +[REVIEW_DELETED_FF]: {{}} +[REVIEW_SW_CSR]: {{}} +[REVIEW_SW_FATAL_ERR]: {{}} +[REVIEW_SW_CHANGE]: {{}} +[REVIEW_SW_ERRATA]: {{}} +[D3_REVIEWED]: {{}} ## Verification Checklist @@ -112,7 +112,7 @@ Review | Signoff date | Not Started | Type | Item | Resolution | Note/Collaterals --------------|---------------------------------------|-------------|------------------ -Documentation | [DV_PLAN_DRAFT_COMPLETED][] | Not Started | +Documentation | [DV_PLAN_DRAFT_COMPLETED][] | Not Started | Documentation | [TESTPLAN_COMPLETED][] | Not Started | Testbench | [TB_TOP_CREATED][] | Not Started | Testbench | [PRELIMINARY_ASSERTION_CHECKS_ADDED][]| Not Started | @@ -134,25 +134,25 @@ Review | Reviewer(s) | Not Started | Review | Signoff date | Not Started | -[DV_PLAN_DRAFT_COMPLETED]: {{}} -[TESTPLAN_COMPLETED]: {{}} -[TB_TOP_CREATED]: {{}} -[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{}} -[TB_ENV_CREATED]: {{}} -[RAL_MODEL_GEN_AUTOMATED]: {{}} -[TB_GEN_AUTOMATED]: {{}} +[TESTPLAN_COMPLETED]: {{}} +[TB_TOP_CREATED]: {{}} +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{}} +[TB_ENV_CREATED]: {{}} +[RAL_MODEL_GEN_AUTOMATED]: {{}} +[TB_GEN_AUTOMATED]: {{}} -[SANITY_TEST_PASSING]: {{}} -[CSR_MEM_TEST_SUITE_PASSING]: {{}} -[ALT_TOOL_SETUP]: {{}} -[SANITY_REGRESSION_SETUP]: {{}} -[NIGHTLY_REGRESSION_SETUP]: {{}} -[COVERAGE_MODEL_ADDED]: {{}} -[PRE_VERIFIED_SUB_MODULES_V1]: {{}} -[DESIGN_SPEC_REVIEWED]: {{}} -[DV_PLAN_TESTPLAN_REVIEWED]: {{}} -[STD_TEST_CATEGORIES_PLANNED]: {{}} -[V2_CHECKLIST_SCOPED]: {{}} +[SANITY_TEST_PASSING]: {{}} +[CSR_MEM_TEST_SUITE_PASSING]: {{}} +[ALT_TOOL_SETUP]: {{}} +[SANITY_REGRESSION_SETUP]: {{}} +[NIGHTLY_REGRESSION_SETUP]: {{}} +[COVERAGE_MODEL_ADDED]: {{}} +[PRE_VERIFIED_SUB_MODULES_V1]: {{}} +[DESIGN_SPEC_REVIEWED]: {{}} +[DV_PLAN_TESTPLAN_REVIEWED]: {{}} +[STD_TEST_CATEGORIES_PLANNED]: {{}} +[V2_CHECKLIST_SCOPED]: {{}} ### Checklists for milestone V2 @@ -176,24 +176,24 @@ Review | Reviewer(s) | Not Started | Review | Signoff date | Not Started | -[DESIGN_DELTAS_CAPTURED]: {{}} -[DV_PLAN_COMPLETED]: {{}} +[DV_PLAN_COMPLETED]: {{}} -[ALL_INTERFACES_EXERCISED]: {{}} -[ALL_ASSERTION_CHECKS_ADDED]: {{}} -[TB_ENV_COMPLETED]: {{}} +[ALL_ASSERTION_CHECKS_ADDED]: {{}} +[TB_ENV_COMPLETED]: {{}} -[ALL_TESTS_PASSING]: {{}} -[FW_SIMULATED]: {{}} -[NIGHTLY_REGRESSION_V2]: {{}} -[CODE_COVERAGE_V2]: {{}} +[NIGHTLY_REGRESSION_V2]: {{}} +[CODE_COVERAGE_V2]: {{}} -[FUNCTIONAL_COVERAGE_V2]: {{}} -[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{}} -[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{}} -[PRE_VERIFIED_SUB_MODULES_V2]: {{}} -[V3_CHECKLIST_SCOPED]: {{}} +[FUNCTIONAL_COVERAGE_V2]: {{}} +[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{}} +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{}} +[PRE_VERIFIED_SUB_MODULES_V2]: {{}} +[V3_CHECKLIST_SCOPED]: {{}} ### Checklists for milestone V3 @@ -211,12 +211,12 @@ Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | Not Started | Review | Reviewer(s) | Not Started | Review | Signoff date | Not Started | -[DESIGN_DELTAS_CAPTURED_IF_ANY]:{{}} -[ALL_TODOS_RESOLVED]: {{}} -[X_PROP_ANALYSIS_COMPLETED]: {{}} -[NIGHTLY_REGRESSION_AT_100]: {{}} -[CODE_COVERAGE_AT_100]: {{}} -[FUNCTIONAL_COVERAGE_AT_100]: {{}} -[NO_ISSUES_PENDING]: {{}} -[NO_TOOL_WARNINGS_THROWN]: {{}} -[PRE_VERIFIED_SUB_MODULES_V3]: {{}} +[DESIGN_DELTAS_CAPTURED_IF_ANY]:{{}} +[ALL_TODOS_RESOLVED]: {{}} +[X_PROP_ANALYSIS_COMPLETED]: {{}} +[NIGHTLY_REGRESSION_AT_100]: {{}} +[CODE_COVERAGE_AT_100]: {{}} +[FUNCTIONAL_COVERAGE_AT_100]: {{}} +[NO_ISSUES_PENDING]: {{}} +[NO_TOOL_WARNINGS_THROWN]: {{}} +[PRE_VERIFIED_SUB_MODULES_V3]: {{}} diff --git a/doc/rm/_index.md b/doc/rm/_index.md index e8afb1d11d348..906c6867a46de 100644 --- a/doc/rm/_index.md +++ b/doc/rm/_index.md @@ -12,5 +12,4 @@ * [Hjson Usage and Style Guide]({{< relref "hjson_usage_style.md" >}}) * [Markdown Usage and Style Guide]({{< relref "markdown_usage_style.md" >}}) * [C/C++ Style Guide]({{< relref "c_cpp_coding_style.md" >}}) - * [Signoff Checklist]({{< relref "checklist.md" >}}) * [FPGA Reference Manua]({{< relref "ref_manual_fpga.md" >}}) diff --git a/doc/rm/c_cpp_coding_style.md b/doc/rm/c_cpp_coding_style.md index 34be6b188bd36..ece50a2e48b3b 100644 --- a/doc/rm/c_cpp_coding_style.md +++ b/doc/rm/c_cpp_coding_style.md @@ -75,6 +75,8 @@ Example: It is recommended to use fully-qualified issue numbers or URLs when referencing issues or pull requests. +TODO comments should not indicate an assignee of the work. + Example: ```c diff --git a/doc/ug/_index.md b/doc/ug/_index.md index f7fe24ade7274..b734024145ae1 100644 --- a/doc/ug/_index.md +++ b/doc/ug/_index.md @@ -2,8 +2,6 @@ title: "User Guides" --- -# User Guides - * Getting Started * [Getting started]({{< relref "getting_started.md" >}}) * [Quickstart]({{< relref "quickstart.md" >}}) @@ -17,7 +15,6 @@ title: "User Guides" * [Getting started with a design]({{< relref "getting_started_design.md" >}}) * *Getting started with verification* (TODO) * [Work with hardware code in external repositories]({{< relref "vendor_hw.md" >}}) -* [Hardware Development Stages]({{< relref "hw_stages.md" >}}) * [Design Methodology]({{< relref "design.md" >}}) * Language and Tool Selection * Comportability and the Importance of Architectural Conformity @@ -29,7 +26,8 @@ title: "User Guides" * CDC Methodology * DFT * Generated Code -* [Design Verification Methodology]({{< relref "dv_methodology.md" >}}) + * FPGA vs ASIC +* [Design Verification Methodology]({{< relref "doc/ug/dv_methodology" >}}) * Language and Tool Selection * Defining Verification Complete: Stages and Checklists * Documentation @@ -50,4 +48,3 @@ title: "User Guides" * How to run tests * How does this differ from verification * How to add tests -* [List of Top-Level Designs]({{< relref "system_list.md" >}}) diff --git a/doc/ug/design.md b/doc/ug/design.md index 99e9e3cc21baa..ef949e5e59d3c 100644 --- a/doc/ug/design.md +++ b/doc/ug/design.md @@ -27,7 +27,7 @@ These are detailed in the [Comportability Specification]({{< relref "doc/rm/comp This document details how peripheral IP interconnects with the embedded processor, the chip IO, other designs, and the security infrastructure within the SOC. Not all of the details are complete at this time, but will be tracked and finalized within that specification. -TODO: briefly discuss key architectural decisions, and how we came to the conclusion, with pointers to more thorough documentation. List? +TODO: briefly discuss key architectural decisions, and how we came to the conclusion, with pointers to more thorough documentation. Some candidates: * Processor/RISC-V strategy * Bus strategy * Reset strategy @@ -37,7 +37,7 @@ TODO: briefly discuss key architectural decisions, and how we came to the conclu Designs within the OpenTitan project come in a variety of completion status levels. Some designs are "tapeout ready" while others are still a work in progress. Understanding the status of a design is important to gauge the confidence in its advertised feature set. -To that end, we've designated a spectrum of design stages in the [OpenTitan Hardware Development Stages]({{< relref "hw_stages.md" >}}) document. +To that end, we've designated a spectrum of design stages in the [OpenTitan Hardware Development Stages]({{< relref "doc/project/hw_stages.md" >}}) document. This document defines the design stages and references where one can find the current status of each of the designs in the repository. ## Documentation @@ -81,7 +81,7 @@ Due to the proprietary nature of this particular linting tool, content towards r In the current state of the project, all lint scripts, policy files, and waivers are **not** provided, but are being kept privately until we can suggest a workable open source solution. When this methodology is finalized the details will be given here. (TODO) -Goals for linting closure per design milestone are given in the [OpenTitan Development Stages]({{< relref "hw_stages.md" >}}) document. +Goals for linting closure per design milestone are given in the [OpenTitan Development Stages]({{< relref "doc/project/hw_stages" >}}) document. ## Assertion Methodology @@ -136,7 +136,7 @@ In this context, our primary concern at this stage is what impact does this have DFT in OpenTitan is particularly interesting for two primary reasons: the RTL in the OpenTitan repository is targeted towards an FPGA implementation, but must be prepared for a silicon implementation -(see the FPGA vs Silicon discussion in the [OpenTitan Product]({{< relref "doc/product.md" >}}) document); +(see the FPGA vs Silicon discussion later in this document); the whole purpose of a DFT methodology is full and efficient access to all logic and storage content, while the whole purpose of a security microcontroller is restricting access to private secured information. In light of the latter dilemma, special care must be taken in a security design to ensure DFT has access at only the appropriate times, but not while in use in production. @@ -164,5 +164,7 @@ This is used by an Azure Pipelines pre-submit check script to ensure that the so ## Getting Started with a Design -The process for getting started with a design involves many steps, including getting clarity on its purpose, its feature set, authorship assignments, documentation, etc. +The process for getting started with a design involves many steps, including getting clarity on its purpose, its feature set, authorship, documentation, etc. These are discussed in the [Getting Started with a Design]({{< relref "getting_started_design.md" >}}) document. + +## FPGA vs Silicon diff --git a/doc/ug/dv_methodology.md b/doc/ug/dv_methodology.md index 7425e5035cb65..9f620d42e9de2 100644 --- a/doc/ug/dv_methodology.md +++ b/doc/ug/dv_methodology.md @@ -35,7 +35,7 @@ Understanding the status of verification is important to gauge the confidence in To that end, we've designated a spectrum of design and verification stages in the [OpenTitan Hardware Development Stages]({{< relref "hw_stages.md" >}}) document. It defines the verification stages and references where one can find the current verification status of each of the designs in the repository. Splitting the effort in such a way enables the team to pace the development effort and allows the progress to be in lock-step with the design stages. -The list of tasks that are required to be completed to enable the effort to transition from one stage to the next is defined in the [checklists]({{< relref "doc/rm/checklist" >}}) document. +The list of tasks that are required to be completed to enable the effort to transition from one stage to the next is defined in the [checklists]({{< relref "doc/project/checklist" >}}) document. Verification is said to be complete when the checklist items for all stages are marked as done. We will explain some of the key items in those checklists in the remainder of this document. diff --git a/doc/ug/getting_started_design.md b/doc/ug/getting_started_design.md index baae77f72a880..51e87c69dead3 100644 --- a/doc/ug/getting_started_design.md +++ b/doc/ug/getting_started_design.md @@ -15,7 +15,7 @@ Feedback and improvements are welcome. ## Stages of a Design -The life stages of a design within the OpenTitan are described in the [Hardware Development Stages]({{< relref "hw_stages.md" >}}) document. +The life stages of a design within the OpenTitan are described in the [Hardware Development Stages]({{< relref "doc/project/hw_stages.md" >}}) document. This separates the life of the design into three broad stages: Specification, In Development, and Signed off. This document attempts to give guidance on how to get going with the first stage and have a smooth transition into the Development stage. They are not hard and fast rules but methods we have seen work well in the project. @@ -33,7 +33,7 @@ Design proposals should follow the recommended [RFC (Request for Comment)]({{< r If the RFC potentially contains information that could be certification-sensitive (guidance to be shared), send a note to security@opentitan.org first for feedback. The OpenTitan Technical Committee may be able to suggest other collaborators to help with early stage review. -An example of a canonical RFC can be found *here* (TODO). +An example of a canonical RFC will be provided *here* (TODO). ## Detailed Specification @@ -80,7 +80,7 @@ This applies only for those specifications that originated on the Drive. ## Full Design -As the design develops within the OpenTitan repo, it transitions into "D0", "D1", etc., [design stages]({{< relref "hw_stages.md" >}}) and will be eventually plugged into the top level. +As the design develops within the OpenTitan repo, it transitions into "D0", "D1", etc., [design stages]({{< relref "doc/project/hw_stages.md" >}}) and will be eventually plugged into the top level. Following the recommended best practices for digestible pull requests suggests that continuing to stage the design from the initial skeleton into the full featured design is a good way to make steady progress without over-burdening the reviewers. ## Top Level Inclusion diff --git a/hw/dv/doc/dv_plan_template.md b/hw/dv/doc/dv_plan_template.md index fa0a2eb2df512..0ec2db25e38f8 100644 --- a/hw/dv/doc/dv_plan_template.md +++ b/hw/dv/doc/dv_plan_template.md @@ -21,7 +21,7 @@ title: "FOO DV Plan" ## Current status * [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) - * [HW development stages]({{< relref "doc/ug/hw_stages" >}}) + * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * DV regression results dashboard (link TBD) ## Design features diff --git a/hw/ip/gpio/doc/dv_plan/index.md b/hw/ip/gpio/doc/dv_plan/index.md index ea8e6d045cd57..204a070c65d0d 100644 --- a/hw/ip/gpio/doc/dv_plan/index.md +++ b/hw/ip/gpio/doc/dv_plan/index.md @@ -11,7 +11,7 @@ title: "GPIO DV Plan" ## Current status * [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) - * [HW development stages]({{< relref "doc/ug/hw_stages" >}}) + * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * DV regression results dashboard (link TBD) ## Design features diff --git a/hw/ip/hmac/doc/dv_plan/index.md b/hw/ip/hmac/doc/dv_plan/index.md index e26a5384298ef..91c25db9601de 100644 --- a/hw/ip/hmac/doc/dv_plan/index.md +++ b/hw/ip/hmac/doc/dv_plan/index.md @@ -11,7 +11,7 @@ title: "HMAC DV Plan" ## Current status * [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) - * [HW development stages]({{< relref "doc/ug/hw_stages" >}}) + * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * DV regression results dashboard (link TBD) ## Design features diff --git a/hw/ip/i2c/doc/dv_plan/index.md b/hw/ip/i2c/doc/dv_plan/index.md index 6279c6fb45336..ec110bfc09aac 100644 --- a/hw/ip/i2c/doc/dv_plan/index.md +++ b/hw/ip/i2c/doc/dv_plan/index.md @@ -11,7 +11,7 @@ title: "I2C DV Plan" ## Current status * [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) - * [HW development stages]({{< relref "doc/ug/hw_stages" >}}) + * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * DV regression results dashboard (link TBD) ## Design features diff --git a/hw/ip/rv_timer/doc/checklist.md b/hw/ip/rv_timer/doc/checklist.md index e92e074cbc018..c39d6a2224892 100644 --- a/hw/ip/rv_timer/doc/checklist.md +++ b/hw/ip/rv_timer/doc/checklist.md @@ -2,9 +2,9 @@ title: "RV_TIMER Checklist" --- -This checklist is for [Hardware Stage]({{}}) +This checklist is for [Hardware Stage]({{}}) transitions for the [rv_timer peripheral.](../) All checklist -items refer to the content in the [Checklist.]({{}}) +items refer to the content in the [Checklist.]({{}}) ## Design Checklist @@ -26,22 +26,22 @@ Review | Signoff date | Done | 2019-10-29 [RV_TIMER Spec]: {{}} -[SPEC_COMPLETE]: {{}} -[CSR_DEFINED]: {{}} -[CLKRST_CONNECTED]: {{}} -[IP_TOP]: {{}} -[IP_INSTANCED]: {{}} -[MEM_INSTANCED_80]: {{}} -[FUNC_IMPLEMENTED]: {{}} -[ASSERT_KNOWN_ADDED]: {{}} -[LINT_SETUP]: {{}} -[D1_REVIEWED]: {{}} +[SPEC_COMPLETE]: {{}} +[CSR_DEFINED]: {{}} +[CLKRST_CONNECTED]: {{}} +[IP_TOP]: {{}} +[IP_INSTANCED]: {{}} +[MEM_INSTANCED_80]: {{}} +[FUNC_IMPLEMENTED]: {{}} +[ASSERT_KNOWN_ADDED]: {{}} +[LINT_SETUP]: {{}} +[D1_REVIEWED]: {{}} ### D2 Type | Item | Resolution | Note/Collaterals --------------|-------------------------|----------------|------------------ -Documentation | [NEW_FEATURES][] | N/A | +Documentation | [NEW_FEATURES][] | N/A | Documentation | [BLOCK_DIAGRAM][] | Done | Documentation | [DOC_INTERFACE][] | Done | Documentation | [MISSING_FUNC][] | N/A | @@ -61,24 +61,24 @@ Review | Signoff date | Done | 2019-10-29 [#68]: https://github.com/lowRISC/opentitan/issues/68 -[NEW_FEATURES]: {{}} -[BLOCK_DIAGRAM]: {{}} -[DOC_INTERFACE]: {{}} -[MISSING_FUNC]: {{}} -[FEATURE_FROZEN]: {{}} -[FEATURE_COMPLETE]: {{}} -[AREA_SANITY_CHECK]: {{}} -[DEBUG_BUS]: {{}} -[PORT_FROZEN]: {{}} -[ARCHITECTURE_FROZEN]: {{}} -[REVIEW_TODO]: {{}} -[STYLE_X]: {{}} -[STYLE_LINT_SETUP]: {{}} -[LINT_PASS]: {{}} -[CDC_SETUP]: {{}} -[CDC_SYNCMACRO]: {{}} -[FPGA_TIMING]: {{}} -[D2_REVIEWED]: {{}} +[NEW_FEATURES]: {{}} +[BLOCK_DIAGRAM]: {{}} +[DOC_INTERFACE]: {{}} +[MISSING_FUNC]: {{}} +[FEATURE_FROZEN]: {{}} +[FEATURE_COMPLETE]: {{}} +[AREA_SANITY_CHECK]: {{}} +[DEBUG_BUS]: {{}} +[PORT_FROZEN]: {{}} +[ARCHITECTURE_FROZEN]: {{}} +[REVIEW_TODO]: {{}} +[STYLE_X]: {{}} +[STYLE_LINT_SETUP]: {{}} +[LINT_PASS]: {{}} +[CDC_SETUP]: {{}} +[CDC_SYNCMACRO]: {{}} +[FPGA_TIMING]: {{}} +[D2_REVIEWED]: {{}} ### D3 @@ -97,18 +97,18 @@ Review | [REVIEW_SW_ERRATA][] | N/A | Review | Reviewer(s) | Done | @tjaychen @sjgitty @shakushw Review | Signoff date | Done | 2019-10-30 -[NEW_FEATURES_D3]: {{}} -[TODO_COMPLETE]: {{}} -[LINT_COMPLETE]: {{}} -[CDC_COMPLETE]: {{}} -[REVIEW_RTL]: {{}} -[REVIEW_DBG]: {{}} -[REVIEW_DELETED_FF]: {{}} -[REVIEW_SW_CSR]: {{}} -[REVIEW_SW_FATAL_ERR]: {{}} -[REVIEW_SW_CHANGE]: {{}} -[REVIEW_SW_ERRATA]: {{}} -[D3_REVIEWED]: {{}} +[NEW_FEATURES_D3]: {{}} +[TODO_COMPLETE]: {{}} +[LINT_COMPLETE]: {{}} +[CDC_COMPLETE]: {{}} +[REVIEW_RTL]: {{}} +[REVIEW_DBG]: {{}} +[REVIEW_DELETED_FF]: {{}} +[REVIEW_SW_CSR]: {{}} +[REVIEW_SW_FATAL_ERR]: {{}} +[REVIEW_SW_CHANGE]: {{}} +[REVIEW_SW_ERRATA]: {{}} +[D3_REVIEWED]: {{}} ## Verification Checklist @@ -138,24 +138,24 @@ Review | Reviewer(s) | Done | @eunch Review | Signoff date | Done | 2019-10-29 -[DV_PLAN_DRAFT_COMPLETED]: {{}} -[TESTPLAN_COMPLETED]: {{}} -[TB_TOP_CREATED]: {{}} -[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{}} -[TB_ENV_CREATED]: {{}} -[RAL_MODEL_GEN_AUTOMATED]: {{}} -[TB_GEN_AUTOMATED]: {{}} -[SANITY_TEST_PASSING]: {{}} -[CSR_MEM_TEST_SUITE_PASSING]: {{}} -[ALT_TOOL_SETUP]: {{}} -[SANITY_REGRESSION_SETUP]: {{}} -[NIGHTLY_REGRESSION_SETUP]: {{}} -[COVERAGE_MODEL_ADDED]: {{}} -[PRE_VERIFIED_SUB_MODULES_V1]: {{}} -[DESIGN_SPEC_REVIEWED]: {{}} -[DV_PLAN_TESTPLAN_REVIEWED]: {{}} -[STD_TEST_CATEGORIES_PLANNED]: {{}} -[V2_CHECKLIST_SCOPED]: {{}} +[DV_PLAN_DRAFT_COMPLETED]: {{}} +[TESTPLAN_COMPLETED]: {{}} +[TB_TOP_CREATED]: {{}} +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{}} +[TB_ENV_CREATED]: {{}} +[RAL_MODEL_GEN_AUTOMATED]: {{}} +[TB_GEN_AUTOMATED]: {{}} +[SANITY_TEST_PASSING]: {{}} +[CSR_MEM_TEST_SUITE_PASSING]: {{}} +[ALT_TOOL_SETUP]: {{}} +[SANITY_REGRESSION_SETUP]: {{}} +[NIGHTLY_REGRESSION_SETUP]: {{}} +[COVERAGE_MODEL_ADDED]: {{}} +[PRE_VERIFIED_SUB_MODULES_V1]: {{}} +[DESIGN_SPEC_REVIEWED]: {{}} +[DV_PLAN_TESTPLAN_REVIEWED]: {{}} +[STD_TEST_CATEGORIES_PLANNED]: {{}} +[V2_CHECKLIST_SCOPED]: {{}} ### V2 @@ -180,20 +180,20 @@ Review | Signoff date | Done | 2019-11- [#69]: https://github.com/lowRISC/opentitan/issues/69 -[DESIGN_DELTAS_CAPTURED]: {{}} -[DV_PLAN_COMPLETED]: {{}} -[ALL_INTERFACES_EXERCISED]: {{}} -[ALL_ASSERTION_CHECKS_ADDED]: {{}} -[TB_ENV_COMPLETED]: {{}} -[ALL_TESTS_PASSING]: {{}} -[FW_SIMULATED]: {{}} -[NIGHTLY_REGRESSION_V2]: {{}} -[CODE_COVERAGE_V2]: {{}} -[FUNCTIONAL_COVERAGE_V2]: {{}} -[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{}} -[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{}} -[PRE_VERIFIED_SUB_MODULES_V2]: {{}} -[V3_CHECKLIST_SCOPED]: {{}} +[DESIGN_DELTAS_CAPTURED]: {{}} +[DV_PLAN_COMPLETED]: {{}} +[ALL_INTERFACES_EXERCISED]: {{}} +[ALL_ASSERTION_CHECKS_ADDED]: {{}} +[TB_ENV_COMPLETED]: {{}} +[ALL_TESTS_PASSING]: {{}} +[FW_SIMULATED]: {{}} +[NIGHTLY_REGRESSION_V2]: {{}} +[CODE_COVERAGE_V2]: {{}} +[FUNCTIONAL_COVERAGE_V2]: {{}} +[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{}} +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{}} +[PRE_VERIFIED_SUB_MODULES_V2]: {{}} +[V3_CHECKLIST_SCOPED]: {{}} ### V3 @@ -214,13 +214,13 @@ Review | Signoff date | Done | 2019-11-04 [#671]: https://github.com/lowRISC/opentitan/pull/671 [#844]: https://github.com/lowRISC/opentitan/pull/844 -[DESIGN_DELTAS_CAPTURED_IF_ANY]:{{}} -[ALL_TODOS_RESOLVED]: {{}} -[X_PROP_ANALYSIS_COMPLETED]: {{}} -[NIGHTLY_REGRESSION_AT_100]: {{}} -[CODE_COVERAGE_AT_100]: {{}} -[FUNCTIONAL_COVERAGE_AT_100]: {{}} -[NO_ISSUES_PENDING]: {{}} -[NO_TOOL_WARNINGS_THROWN]: {{}} -[PRE_VERIFIED_SUB_MODULES_V3]: {{}} +[DESIGN_DELTAS_CAPTURED_IF_ANY]:{{}} +[ALL_TODOS_RESOLVED]: {{}} +[X_PROP_ANALYSIS_COMPLETED]: {{}} +[NIGHTLY_REGRESSION_AT_100]: {{}} +[CODE_COVERAGE_AT_100]: {{}} +[FUNCTIONAL_COVERAGE_AT_100]: {{}} +[NO_ISSUES_PENDING]: {{}} +[NO_TOOL_WARNINGS_THROWN]: {{}} +[PRE_VERIFIED_SUB_MODULES_V3]: {{}} diff --git a/hw/ip/rv_timer/doc/dv_plan/index.md b/hw/ip/rv_timer/doc/dv_plan/index.md index cddabeffe66fd..3a3a50b7c56f5 100644 --- a/hw/ip/rv_timer/doc/dv_plan/index.md +++ b/hw/ip/rv_timer/doc/dv_plan/index.md @@ -11,7 +11,7 @@ title: "RV_TIMER DV Plan" ## Current status * [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) - * [HW development stages]({{< relref "doc/ug/hw_stages" >}}) + * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * DV regression results dashboard (link TBD) ## Design features diff --git a/hw/ip/uart/doc/checklist.md b/hw/ip/uart/doc/checklist.md index 67a56db626e55..0d0252f9dfd14 100644 --- a/hw/ip/uart/doc/checklist.md +++ b/hw/ip/uart/doc/checklist.md @@ -3,9 +3,9 @@ title: "UART Checklist" --- This checklist is for [Hardware Stage][] transitions for the [UART peripheral.](../) -All checklist items refer to the content in the [Checklist.]({{}}) +All checklist items refer to the content in the [Checklist.]({{}}) -[Hardware Stage]: {{}} +[Hardware Stage]: {{}} ## Design Checklist @@ -27,15 +27,15 @@ Review | Reviewer(s) | Done | @weicaiyang @sjgitty Review | Signoff date | Done | 2019-10-28 -[SPEC_COMPLETE]: {{}} -[CSR_DEFINED]: {{}} -[CLKRST_CONNECTED]: {{}} -[IP_TOP]: {{}} -[IP_INSTANCED]: {{}} -[MEM_INSTANCED_80]: {{}} -[FUNC_IMPLEMENTED]: {{}} -[ASSERT_KNOWN_ADDED]: {{}} -[LINT_SETUP]: {{}} +[SPEC_COMPLETE]: {{}} +[CSR_DEFINED]: {{}} +[CLKRST_CONNECTED]: {{}} +[IP_TOP]: {{}} +[IP_INSTANCED]: {{}} +[MEM_INSTANCED_80]: {{}} +[FUNC_IMPLEMENTED]: {{}} +[ASSERT_KNOWN_ADDED]: {{}} +[LINT_SETUP]: {{}} ### D1 Exceptions @@ -45,7 +45,7 @@ Review | Signoff date | Done | 2019-10-28 Type | Item | Resolution | Note/Collaterals --------------|-------------------------|-------------|------------------ -Documentation | [NEW_FEATURES][] | N/A | +Documentation | [NEW_FEATURES][] | N/A | Documentation | [BLOCK_DIAGRAM][] | N/A | Documentation | [DOC_INTERFACE][] | Done | Documentation | [MISSING_FUNC][] | N/A | @@ -63,23 +63,23 @@ Code Quality | [CDC_SYNCMACRO][] | N/A | Review | Reviewer(s) | Done | @msfschaffner @weicaiyang @sriyerg @sjgitty Review | Signoff date | Done | 2019-10-28 -[NEW_FEATURES]: {{}} -[BLOCK_DIAGRAM]: {{}} -[DOC_INTERFACE]: {{}} -[MISSING_FUNC]: {{}} -[FEATURE_FROZEN]: {{}} -[FEATURE_COMPLETE]: {{}} -[AREA_SANITY_CHECK]: {{}} -[DEBUG_BUS]: {{}} -[PORT_FROZEN]: {{}} -[ARCHITECTURE_FROZEN]: {{}} -[REVIEW_TODO]: {{}} -[STYLE_X]: {{}} -[STYLE_LINT_SETUP]: {{}} -[LINT_PASS]: {{}} -[CDC_SETUP]: {{}} -[CDC_SYNCMACRO]: {{}} -[FPGA_TIMING]: {{}} +[NEW_FEATURES]: {{}} +[BLOCK_DIAGRAM]: {{}} +[DOC_INTERFACE]: {{}} +[MISSING_FUNC]: {{}} +[FEATURE_FROZEN]: {{}} +[FEATURE_COMPLETE]: {{}} +[AREA_SANITY_CHECK]: {{}} +[DEBUG_BUS]: {{}} +[PORT_FROZEN]: {{}} +[ARCHITECTURE_FROZEN]: {{}} +[REVIEW_TODO]: {{}} +[STYLE_X]: {{}} +[STYLE_LINT_SETUP]: {{}} +[LINT_PASS]: {{}} +[CDC_SETUP]: {{}} +[CDC_SYNCMACRO]: {{}} +[FPGA_TIMING]: {{}} ### D3 @@ -98,17 +98,17 @@ Review | [REVIEW_SW_ERRATA][] | Done | Review | Reviewer(s) | Done | @weicaiyang @sjgitty @msfschaffner Review | Signoff date | Done | 2019-10-31 -[NEW_FEATURES_D3]: {{}} -[TODO_COMPLETE]: {{}} -[LINT_COMPLETE]: {{}} -[CDC_COMPLETE]: {{}} -[REVIEW_RTL]: {{}} -[REVIEW_DBG]: {{}} -[REVIEW_DELETED_FF]: {{}} -[REVIEW_SW_CSR]: {{}} -[REVIEW_SW_FATAL_ERR]: {{}} -[REVIEW_SW_CHANGE]: {{}} -[REVIEW_SW_ERRATA]: {{}} +[NEW_FEATURES_D3]: {{}} +[TODO_COMPLETE]: {{}} +[LINT_COMPLETE]: {{}} +[CDC_COMPLETE]: {{}} +[REVIEW_RTL]: {{}} +[REVIEW_DBG]: {{}} +[REVIEW_DELETED_FF]: {{}} +[REVIEW_SW_CSR]: {{}} +[REVIEW_SW_FATAL_ERR]: {{}} +[REVIEW_SW_CHANGE]: {{}} +[REVIEW_SW_ERRATA]: {{}} ## Verification Checklist @@ -137,24 +137,24 @@ Review | Reviewer(s) | Done | @eunchan @ Review | Signoff date | Done | 2019-10-28 -[DV_PLAN_DRAFT_COMPLETED]: {{}} -[TESTPLAN_COMPLETED]: {{}} -[TB_TOP_CREATED]: {{}} -[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{}} -[TB_ENV_CREATED]: {{}} -[RAL_MODEL_GEN_AUTOMATED]: {{}} -[TB_GEN_AUTOMATED]: {{}} -[SANITY_TEST_PASSING]: {{}} -[CSR_MEM_TEST_SUITE_PASSING]: {{}} -[ALT_TOOL_SETUP]: {{}} -[SANITY_REGRESSION_SETUP]: {{}} -[NIGHTLY_REGRESSION_SETUP]: {{}} -[COVERAGE_MODEL_ADDED]: {{}} -[PRE_VERIFIED_SUB_MODULES_V1]: {{}} -[DESIGN_SPEC_REVIEWED]: {{}} -[DV_PLAN_TESTPLAN_REVIEWED]: {{}} -[STD_TEST_CATEGORIES_PLANNED]: {{}} -[V2_CHECKLIST_SCOPED]: {{}} +[DV_PLAN_DRAFT_COMPLETED]: {{}} +[TESTPLAN_COMPLETED]: {{}} +[TB_TOP_CREATED]: {{}} +[PRELIMINARY_ASSERTION_CHECKS_ADDED]: {{}} +[TB_ENV_CREATED]: {{}} +[RAL_MODEL_GEN_AUTOMATED]: {{}} +[TB_GEN_AUTOMATED]: {{}} +[SANITY_TEST_PASSING]: {{}} +[CSR_MEM_TEST_SUITE_PASSING]: {{}} +[ALT_TOOL_SETUP]: {{}} +[SANITY_REGRESSION_SETUP]: {{}} +[NIGHTLY_REGRESSION_SETUP]: {{}} +[COVERAGE_MODEL_ADDED]: {{}} +[PRE_VERIFIED_SUB_MODULES_V1]: {{}} +[DESIGN_SPEC_REVIEWED]: {{}} +[DV_PLAN_TESTPLAN_REVIEWED]: {{}} +[STD_TEST_CATEGORIES_PLANNED]: {{}} +[V2_CHECKLIST_SCOPED]: {{}} ### Checklists for milestone V2 Type | Item | Resolution | Note/Collaterals @@ -177,20 +177,20 @@ Review | Reviewer(s) | Done | @eunchan Review | Signoff date | Done | 2019-10-28 -[DESIGN_DELTAS_CAPTURED]: {{}} -[DV_PLAN_COMPLETED]: {{}} -[ALL_INTERFACES_EXERCISED]: {{}} -[ALL_ASSERTION_CHECKS_ADDED]: {{}} -[TB_ENV_COMPLETED]: {{}} -[ALL_TESTS_PASSING]: {{}} -[FW_SIMULATED]: {{}} -[NIGHTLY_REGRESSION_V2]: {{}} -[CODE_COVERAGE_V2]: {{}} -[FUNCTIONAL_COVERAGE_V2]: {{}} -[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{}} -[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{}} -[PRE_VERIFIED_SUB_MODULES_V2]: {{}} -[V3_CHECKLIST_SCOPED]: {{}} +[DESIGN_DELTAS_CAPTURED]: {{}} +[DV_PLAN_COMPLETED]: {{}} +[ALL_INTERFACES_EXERCISED]: {{}} +[ALL_ASSERTION_CHECKS_ADDED]: {{}} +[TB_ENV_COMPLETED]: {{}} +[ALL_TESTS_PASSING]: {{}} +[FW_SIMULATED]: {{}} +[NIGHTLY_REGRESSION_V2]: {{}} +[CODE_COVERAGE_V2]: {{}} +[FUNCTIONAL_COVERAGE_V2]: {{}} +[NO_HIGH_PRIORITY_ISSUES_PENDING]: {{}} +[ALL_LOW_PRIORITY_ISSUES_ROOT_CAUSED]:{{}} +[PRE_VERIFIED_SUB_MODULES_V2]: {{}} +[V3_CHECKLIST_SCOPED]: {{}} ### Checklists for milestone V3 Type | Item | Resolution | Note/Collaterals @@ -207,14 +207,14 @@ Integration | [PRE_VERIFIED_SUB_MODULES_V3][] | N/A | Review | Reviewer(s) | Done | @eunchan @sjgitty @sriyerg Review | Signoff date | Done | 2019-11-01 -[DESIGN_DELTAS_CAPTURED_IF_ANY]:{{}} -[ALL_TODOS_RESOLVED]: {{}} -[X_PROP_ANALYSIS_COMPLETED]: {{}} -[NIGHTLY_REGRESSION_AT_100]: {{}} -[CODE_COVERAGE_AT_100]: {{}} -[FUNCTIONAL_COVERAGE_AT_100]: {{}} -[NO_ISSUES_PENDING]: {{}} -[NO_TOOL_WARNINGS_THROWN]: {{}} -[PRE_VERIFIED_SUB_MODULES_V3]: {{}} +[DESIGN_DELTAS_CAPTURED_IF_ANY]:{{}} +[ALL_TODOS_RESOLVED]: {{}} +[X_PROP_ANALYSIS_COMPLETED]: {{}} +[NIGHTLY_REGRESSION_AT_100]: {{}} +[CODE_COVERAGE_AT_100]: {{}} +[FUNCTIONAL_COVERAGE_AT_100]: {{}} +[NO_ISSUES_PENDING]: {{}} +[NO_TOOL_WARNINGS_THROWN]: {{}} +[PRE_VERIFIED_SUB_MODULES_V3]: {{}} [common_cov_excl.el]:https://github.com/lowRISC/opentitan/blob/master/hw/dv/tools/vcs/common_cov_excl.el [uart_cov_excl.el]: https://github.com/lowRISC/opentitan/blob/04bb36e0ae1430262b048d400102b0fed43377ac/hw/ip/uart/dv/cov/uart_cov_excl.el diff --git a/hw/ip/uart/doc/dv_plan/index.md b/hw/ip/uart/doc/dv_plan/index.md index 2cdd7441fc2d0..b271450ac639b 100644 --- a/hw/ip/uart/doc/dv_plan/index.md +++ b/hw/ip/uart/doc/dv_plan/index.md @@ -12,7 +12,7 @@ title: "UART DV Plan" ## Current status * [Design & verification stage]({{< relref "doc/project/hw_dashboard" >}}) - * [HW development stages]({{< relref "doc/ug/hw_stages" >}}) + * [HW development stages]({{< relref "doc/project/hw_stages.md" >}}) * DV regression results dashboard (link TBD) ## Design features diff --git a/util/testplanner/README.md b/util/testplanner/README.md index a5d06caba5858..94541d6c04027 100644 --- a/util/testplanner/README.md +++ b/util/testplanner/README.md @@ -44,7 +44,7 @@ intent of a planned test: * **tests: list of actual written tests that maps to this planned test** Testplans are written very early in the V0 stage of the HW development - [life-cycle]({{< relref "doc/ug/hw_stages" >}}). When the DV engineer gets to actually + [life-cycle]({{< relref "doc/project/hw_stages.md" >}}). When the DV engineer gets to actually developing the test, it may not map 1:1 to the planned test - it may be possible that an already written test that mapped to another planned test also satisfies the current one; OR it may also be possible that the planned test needs to be diff --git a/util/uvmdvgen/dv_plan.md.tpl b/util/uvmdvgen/dv_plan.md.tpl index 3e61430e33a43..2e404b717d2a6 100644 --- a/util/uvmdvgen/dv_plan.md.tpl +++ b/util/uvmdvgen/dv_plan.md.tpl @@ -21,7 +21,7 @@ ${'##'} Goals ${'##'} Current status * [Design & verification stage](../../../../doc/project/hw_dashboard.md) - * [HW development stages](../../../../doc/ug/hw_stages.md) + * [HW development stages](../../../../doc/project/hw_stages.md) * DV regression results dashboard (link TBD) ${'##'} Design features