From df4d7d58a86b24db28ba483ceead796a5b23fe9d Mon Sep 17 00:00:00 2001 From: Rupert Swarbrick Date: Fri, 3 May 2024 17:28:58 +0100 Subject: [PATCH] [prim] Remove prim_clock_gp_mux2 This prim actually had a bug in a generator function (found and fixed by jwnrt) and wasn't used anywhere. There's no real reason to keep the module around, especially since it hasn't been used since it was added in 2022. Remove it. Signed-off-by: Rupert Swarbrick --- SUMMARY.md | 1 - hw/ip/prim/doc/prim_clock_gp_mux2.md | 26 ------------ hw/ip/prim/prim_clock_gp_mux2.core | 19 --------- hw/ip/prim/rtl/prim_clock_gp_mux2.sv | 62 ---------------------------- 4 files changed, 108 deletions(-) delete mode 100644 hw/ip/prim/doc/prim_clock_gp_mux2.md delete mode 100644 hw/ip/prim/prim_clock_gp_mux2.core delete mode 100644 hw/ip/prim/rtl/prim_clock_gp_mux2.sv diff --git a/SUMMARY.md b/SUMMARY.md index a01245b99db31..9e7a4c2f89711 100644 --- a/SUMMARY.md +++ b/SUMMARY.md @@ -368,7 +368,6 @@ - [Device Interface Functions](./sw/device/lib/dif/dif_usbdev.h) - [Checklist](./hw/ip/usbdev/doc/checklist.md) - [lowRISC Hardware Primitives](./hw/ip/prim/README.md) - - [Two Input Clock](./hw/ip/prim/doc/prim_clock_gp_mux2.md) - [Flash Wrapper](./hw/ip/prim/doc/prim_flash.md) - [Keccak Permutation](./hw/ip/prim/doc/prim_keccak.md) - [Linear Feedback Shift Register](./hw/ip/prim/doc/prim_lfsr.md) diff --git a/hw/ip/prim/doc/prim_clock_gp_mux2.md b/hw/ip/prim/doc/prim_clock_gp_mux2.md deleted file mode 100644 index b73a288e419dc..0000000000000 --- a/hw/ip/prim/doc/prim_clock_gp_mux2.md +++ /dev/null @@ -1,26 +0,0 @@ -# Primitive Component: Two input clock Mux with glitch protection - -# Overview -`prim_clock_gp_mux2` is a two input clock mux that protects a glitch. When a current clock source is switched to the next clock source where two clocks are totally unrelated, a glitch can be generated as follows. - -### Glitch -```wavejson -{signal: [ - {name: 'clk0_i', wave: 'L.H....L....H....L....H....'}, - {name: 'clk1_i', wave: 'L.H.L.H.L.H.L.H.L.H.L.H.L.H'}, - {name: 'sel_i', wave: '0............1.............'}, - {name: 'clk_o', wave: 'L.H....L....HLH.L.H.L.H.L.H'}, - ]} -``` - -This glitch free clock mux can avoid glitch by placing two parallel synchronizers connected to each other. 1st flop and 2nd flop are triggered by positive edge and negative edge respectively to protect metastability on the sel_i signal. The following waveform shows the result. - -### Glitch Free -```wavejson -{signal: [ - {name: 'clk0_i', wave: 'L.H....L....H....L....H....'}, - {name: 'clk1_i', wave: 'L.H.L.H.L.H.L.H.L.H.L.H.L.H'}, - {name: 'sel_i', wave: '0............1.............'}, - {name: 'clk_o', wave: 'L.H....L....H....LH.L.H.L.H'}, - ]} -``` diff --git a/hw/ip/prim/prim_clock_gp_mux2.core b/hw/ip/prim/prim_clock_gp_mux2.core deleted file mode 100644 index 2c9894d4651d1..0000000000000 --- a/hw/ip/prim/prim_clock_gp_mux2.core +++ /dev/null @@ -1,19 +0,0 @@ -CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). -# Licensed under the Apache License, Version 2.0, see LICENSE for details. -# SPDX-License-Identifier: Apache-2.0 - -name: "lowrisc:prim:clock_gp_mux2" -description: "2-input glitch free clock multiplexer" -filesets: - files_rtl: - depend: - - lowrisc:prim:prim_pkg - files: - - rtl/prim_clock_gp_mux2.sv - file_type: systemVerilogSource - -targets: - default: - filesets: - - files_rtl diff --git a/hw/ip/prim/rtl/prim_clock_gp_mux2.sv b/hw/ip/prim/rtl/prim_clock_gp_mux2.sv deleted file mode 100644 index ac259ab863f1b..0000000000000 --- a/hw/ip/prim/rtl/prim_clock_gp_mux2.sv +++ /dev/null @@ -1,62 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 - -// Glitch free clock mux using parallel two flop synchronizers - -module prim_clock_gp_mux2 #( - parameter bit NoFpgaBufG = 1'b0, - parameter bit FpgaBufGlobal = 1, - parameter bit GlitchProtect = 1 -) ( - input clk0_i, - input clk1_i, - input sel_i, - input rst_ni, - input test_en_i, - output logic clk_o -); - -logic [1:0] clk_gp; -logic [1:0] intq; -logic [1:0] stage_d; -logic [1:0] stage_q; -logic [1:0] clk_glitch_off; - -assign clk_gp = {clk1_i, clk0_i}; -assign stage_d = {sel_i & !stage_q[0], !sel_i & !stage_q[1]}; - -generate - genvar i; - for (i = 0; i < 2; i++) begin: gen_two_flops - always_ff @(posedge clk_gp[i] or negedge rst_ni) begin: stage1 - if (!rst_ni) begin - intq[i] <= 1'b0; - end else begin - intq[i] <= stage_d[i]; - end - end - - always_ff @(negedge clk_gp[i] or negedge rst_ni) begin: stage2 - if (!rst_ni) begin - stage_q[i] <= 1'b0; - end else begin - stage_q[i] <= intq[i]; - end - end - - prim_clock_gating #( - .FpgaBufGlobal(FpgaBufGlobal) - ) u_cg ( - .clk_i(clk_gp[i]), - .en_i(stage_q[i]), - .test_en_i(1'b0), - .clk_o(clk_glitch_off[i]) - ); - - end -endgenerate - -assign clk_o = |clk_glitch_off; - -endmodule