From c5ce570e9ef0ba2bab7c7a251b57b408548e9980 Mon Sep 17 00:00:00 2001 From: Alex Jones Date: Fri, 6 Sep 2024 11:47:43 +0100 Subject: [PATCH] [ci, sival] Fix validation errors on testplans Validation can be verified using the commands: ``` ./util/validate_testplans.py --schema hw/lint/sival_testplan_schema.hjson \ --dir hw/top_earlgrey/data ./util/validate_testplans.py --schema hw/lint/sival_testplan_schema.hjson \ --dir hw/top_earlgrey/data/ip ``` Signed-off-by: Alex Jones --- hw/top_earlgrey/data/chip_testplan.hjson | 9 ++++++++ .../data/ip/chip_adc_ctrl_testplan.hjson | 4 ++++ .../data/ip/chip_aes_testplan.hjson | 3 +++ .../data/ip/chip_alert_handler_testplan.hjson | 4 ++++ .../data/ip/chip_flash_ctrl_testplan.hjson | 2 ++ .../data/ip/chip_keymgr_testplan.hjson | 1 + .../data/ip/chip_kmac_testplan.hjson | 1 + .../data/ip/chip_lc_ctrl_testplan.hjson | 2 ++ .../data/ip/chip_otp_ctrl_testplan.hjson | 5 +++++ .../data/ip/chip_rom_ctrl_testplan.hjson | 1 + .../data/ip/chip_rv_core_ibex_testplan.hjson | 1 + .../data/ip/chip_rv_dm_testplan.hjson | 22 +++++++++---------- .../data/ip/chip_spi_host_testplan.hjson | 2 ++ .../data/standalone_sw_testplan.hjson | 6 +++++ 14 files changed, 52 insertions(+), 11 deletions(-) diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson index 297b906980bdb..39808604ee03f 100644 --- a/hw/top_earlgrey/data/chip_testplan.hjson +++ b/hw/top_earlgrey/data/chip_testplan.hjson @@ -110,6 +110,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_padctrl_attributes"] + bazel: [] } { name: chip_padctrl_attributes @@ -129,6 +130,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_padctrl_attributes"] + bazel: [] } { name: chip_sw_sleep_pin_mio_dio_val @@ -171,6 +173,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_sleep_pin_wake"] + bazel: [] } { name: chip_sw_sleep_pin_retention @@ -371,6 +374,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_ast_clk_rst_inputs"] + bazel: [] } { name: chip_sw_ast_sys_clk_jitter @@ -391,6 +395,7 @@ "chip_sw_kmac_mode_kmac_jitter_en", "chip_sw_sram_ctrl_scrambled_access_jitter_en", "chip_sw_edn_entropy_reqs_jitter"] + bazel: [] } { name: chip_sw_ast_usb_clk_calib @@ -411,6 +416,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_usb_ast_clk_calib"] + bazel: [] } // SENSOR_CTRL tests: @@ -442,6 +448,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_sensor_ctrl_status"] + bazel: [] } { name: chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup @@ -453,6 +460,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup"] + bazel: [] } //////////////////////////// @@ -735,6 +743,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_power_sleep_load"] + bazel: [] } { diff --git a/hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson index 719b2b40d4e38..f444d5b990461 100644 --- a/hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_adc_ctrl_testplan.hjson @@ -29,6 +29,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_adc_ctrl_sleep_debug_cable_wakeup"] + bazel: [] } { name: chip_sw_adc_ctrl_sleep_debug_cable_wakeup @@ -54,6 +55,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_adc_ctrl_sleep_debug_cable_wakeup"] + bazel: [] } { name: chip_sw_adc_ctrl_normal @@ -63,6 +65,7 @@ si_stage: SV2 lc_states: ["PROD"] tests: [] + bazel: [] } { name: chip_sw_adc_ctrl_oneshot @@ -72,6 +75,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: [] + bazel: [] } ] } diff --git a/hw/top_earlgrey/data/ip/chip_aes_testplan.hjson b/hw/top_earlgrey/data/ip/chip_aes_testplan.hjson index d41a200e2bc0b..dcdc63d39e6b7 100644 --- a/hw/top_earlgrey/data/ip/chip_aes_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_aes_testplan.hjson @@ -112,6 +112,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: [] + bazel: [] } { name: chip_sw_aes_entropy @@ -180,6 +181,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_aes_prng_reseed"] + bazel: [] } { name: chip_sw_aes_force_prng_reseed @@ -213,6 +215,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_aes_force_prng_reseed"] + bazel: [] } { name: chip_sw_aes_idle diff --git a/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson b/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson index e660717b4eb45..5178ee794e963 100644 --- a/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_alert_handler_testplan.hjson @@ -43,6 +43,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_alert_handler_escalation"] + bazel: [] otp_mutate: true host_support: true } @@ -67,6 +68,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: [] + bazel: [] otp_mutate: false } { @@ -85,6 +87,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: [] + bazel: [] } { name: chip_sw_all_escalation_resets @@ -190,6 +193,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_alert_handler_lpg_sleep_mode_alerts"] + bazel: [] } { name: chip_sw_alert_handler_lpg_sleep_mode_pings diff --git a/hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson index a7a8fb1057653..06f195cb8f993 100644 --- a/hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_flash_ctrl_testplan.hjson @@ -94,6 +94,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_flash_rma_unlocked"] + bazel: [] } { name: chip_sw_flash_scramble @@ -251,6 +252,7 @@ lc_states: ["DEV", "PROD", "PROD_END", "RMA"] boot_stages: ["rom_ext"] tests: ["chip_sw_flash_ctrl_lc_rw_en"] + bazel: [] } { name: chip_sw_flash_lc_escalate_en diff --git a/hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson b/hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson index 75f58c7ec76a1..ae58f76540ba8 100644 --- a/hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_keymgr_testplan.hjson @@ -43,6 +43,7 @@ "chip_sw_keymgr_key_derivation", "chip_sw_keymgr_key_derivation_jitter_en", ] + bazel: [] } { name: chip_sw_keymgr_sideload_kmac_error diff --git a/hw/top_earlgrey/data/ip/chip_kmac_testplan.hjson b/hw/top_earlgrey/data/ip/chip_kmac_testplan.hjson index fa1347c614a53..f7b8faa9cb809 100644 --- a/hw/top_earlgrey/data/ip/chip_kmac_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_kmac_testplan.hjson @@ -96,6 +96,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["chip_sw_kmac_entropy"] + bazel: [] } { name: chip_sw_kmac_idle diff --git a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson index 467e7de9d059c..154e70d40a12c 100644 --- a/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_lc_ctrl_testplan.hjson @@ -288,11 +288,13 @@ Verify that the features that should indeed be disabled are indeed disabled. ''' stage: V2 + si_stage: None tests: ["chip_sw_lc_walkthrough_dev", "chip_sw_lc_walkthrough_prod", "chip_sw_lc_walkthrough_prodend", "chip_sw_lc_walkthrough_rma", "chip_sw_lc_walkthrough_testunlocks"] + bazel: [] } { name: chip_sw_lc_ctrl_volatile_raw_unlock diff --git a/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson index 8debc4c16fde6..c75c23aeee626 100644 --- a/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_otp_ctrl_testplan.hjson @@ -48,6 +48,7 @@ "chip_sw_keymgr_key_derivation", "chip_sw_otbn_mem_scramble", "chip_sw_rv_core_ibex_icache_invalidate"] + bazel: [] } { name: chip_sw_otp_ctrl_entropy @@ -68,6 +69,7 @@ "chip_sw_keymgr_key_derivation", "chip_sw_otbn_mem_scramble", "chip_sw_rv_core_ibex_icache_invalidate"] + bazel: [] } { name: chip_sw_otp_ctrl_program @@ -90,6 +92,7 @@ si_stage: SV1 lc_states: ["PROD"] tests: ["chip_sw_lc_ctrl_transition"] + bazel: [] } { name: chip_sw_otp_ctrl_program_error @@ -180,6 +183,7 @@ si_stage: SV3 lc_states: ["TEST_UNLOCKED", "RMA"] tests: ["chip_prim_tl_access"] + bazel: [] } { name: chip_sw_otp_ctrl_vendor_test_csr_access @@ -232,6 +236,7 @@ si_stage: SV1 lc_states: ["TEST_UNLOCKED"] tests: [] + bazel: [] } { name: otp_ctrl_partition_access_locked diff --git a/hw/top_earlgrey/data/ip/chip_rom_ctrl_testplan.hjson b/hw/top_earlgrey/data/ip/chip_rom_ctrl_testplan.hjson index 33948d8dd842d..4fc03ec87b6a2 100644 --- a/hw/top_earlgrey/data/ip/chip_rom_ctrl_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_rom_ctrl_testplan.hjson @@ -77,6 +77,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: [] + bazel: [] } ] } diff --git a/hw/top_earlgrey/data/ip/chip_rv_core_ibex_testplan.hjson b/hw/top_earlgrey/data/ip/chip_rv_core_ibex_testplan.hjson index ea938cdef102a..7e55ff1248021 100644 --- a/hw/top_earlgrey/data/ip/chip_rv_core_ibex_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_rv_core_ibex_testplan.hjson @@ -222,6 +222,7 @@ stage: V2S si_stage: None tests: ["chip_sw_rv_core_ibex_lockstep_glitch"] + bazel: [] } { name: chip_sw_rv_core_ibex_alerts diff --git a/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson b/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson index 4e614922625ab..cbb663d2aad09 100644 --- a/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_rv_dm_testplan.hjson @@ -24,7 +24,7 @@ tests: ["chip_jtag_csr_rw"] bazel: ["//sw/device/tests:rv_dm_csr_rw"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM" @@ -55,7 +55,7 @@ tests: ["chip_jtag_mem_access"] bazel: ["//sw/device/tests:rv_dm_mem_access"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM", @@ -95,7 +95,7 @@ "rom_e2e_jtag_debug_rma"] bazel: ["//sw/device/silicon_creator/rom/e2e/jtag_inject:rom_e2e_openocd_debug_test"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM", @@ -119,7 +119,7 @@ tests: ["chip_rv_dm_ndm_reset_req"] bazel: ["//sw/device/tests:rv_dm_ndm_reset_req"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM", @@ -151,7 +151,7 @@ tests: ["chip_sw_rv_dm_ndm_reset_req_when_cpu_halted"] bazel: ["//sw/device/tests:rv_dm_ndm_reset_req_when_cpu_halted"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM", @@ -172,7 +172,7 @@ tests: ["chip_sw_rv_dm_access_after_wakeup"] bazel: ["//sw/device/tests:rv_dm_access_after_wakeup"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM" @@ -209,7 +209,7 @@ tests: ["chip_tap_straps_rma"] bazel: ["//sw/device/tests:rv_dm_jtag_tap_sel"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM" @@ -255,7 +255,7 @@ ], lc_states: ["RAW", "TEST_LOCKED", "TEST_UNLOCKED", "DEV", "RMA", "PROD", "PROD_END", "SCRAP"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM" @@ -275,7 +275,7 @@ tests: [] bazel: ["//sw/device/tests:rv_dm_jtag"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", ] @@ -294,7 +294,7 @@ tests: [] bazel: ["//sw/device/tests:rv_dm_dtm"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM", @@ -323,7 +323,7 @@ tests: [] bazel: ["//sw/device/tests:rv_dm_control_status"], lc_states: ["DEV"] - host_support: "true" + host_support: true features: [ "RV_DM.JTAG.FSM", "RV_DM.JTAG.DTM", diff --git a/hw/top_earlgrey/data/ip/chip_spi_host_testplan.hjson b/hw/top_earlgrey/data/ip/chip_spi_host_testplan.hjson index 602ad3cc64cba..2b573ef4eb73b 100644 --- a/hw/top_earlgrey/data/ip/chip_spi_host_testplan.hjson +++ b/hw/top_earlgrey/data/ip/chip_spi_host_testplan.hjson @@ -54,6 +54,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["//sw/device/tests:spi_passthru_test"] + bazel: [] } { name: chip_sw_spi_host_configuration @@ -70,6 +71,7 @@ si_stage: SV3 lc_states: ["PROD"] tests: ["//sw/device/tests:spi_host_config_test"] + bazel: [] } { name: chip_sw_spi_host_events diff --git a/hw/top_earlgrey/data/standalone_sw_testplan.hjson b/hw/top_earlgrey/data/standalone_sw_testplan.hjson index ddc95ecbffe41..4c57eee1177d0 100644 --- a/hw/top_earlgrey/data/standalone_sw_testplan.hjson +++ b/hw/top_earlgrey/data/standalone_sw_testplan.hjson @@ -12,7 +12,9 @@ It also performs a sanity region protection check to make sure a protected page cannot be modified. When the test passes, it will output "PASS!".''' stage: V1 + si_stage: SV4 tests: ["flash_test"] + bazel: [] } { name: hmac @@ -20,7 +22,9 @@ It computes the hash of a known input and compares it against the known digest. When the test passes, it will output "PASS!".''' stage: V1 + si_stage: SV4 tests: ["sha256_test"] + bazel: [] } { name: rv_timer @@ -29,7 +33,9 @@ If the interrupt handling is incorrect, the test will never complete. When the test passes, it will output "PASS!".''' stage: V1 + si_stage: SV4 tests: ["rv_timer_test"] + bazel: [] } ] }