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Reporting Script #14

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veronia-iskandar opened this issue May 30, 2021 · 0 comments
Open

Reporting Script #14

veronia-iskandar opened this issue May 30, 2021 · 0 comments
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To do
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FPGA Design Flow

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@veronia-iskandar
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Report on utilization of the current device, information about clock nets in the design, RAM resources utilized in the implemented design. The script should also perform timing analysis, report on highest fanout of nets in the implemented design, and details of the IO banks in the design. Finally, design rule checking (DRC) should be performed.
@veronia-iskandar veronia-iskandar added the enhancement New feature or request label May 30, 2021
@veronia-iskandar veronia-iskandar added this to the FPGA Design Flow milestone May 30, 2021
@veronia-iskandar veronia-iskandar added To do and removed enhancement New feature or request labels Jun 7, 2021
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