forked from AI-Vector-Accelerator/core-v-verif-ava
-
Notifications
You must be signed in to change notification settings - Fork 0
/
riscv-compliance.patch
63 lines (57 loc) · 2.3 KB
/
riscv-compliance.patch
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
diff --git a/riscv-test-env/v/vm.c b/riscv-test-env/v/vm.c
index 6ab7fd1..fc01b94 100644
--- a/riscv-test-env/v/vm.c
+++ b/riscv-test-env/v/vm.c
@@ -9,8 +9,8 @@
void trap_entry();
void pop_tf(trapframe_t*);
-volatile uint64_t tohost;
-volatile uint64_t fromhost;
+extern volatile uint64_t tohost;
+extern volatile uint64_t fromhost;
static void do_tohost(uint64_t tohost_value)
{
diff --git a/riscv-test-suite/rv32i/src/I-EBREAK-01.S b/riscv-test-suite/rv32i/src/I-EBREAK-01.S
index 958eebc..b84559f 100644
--- a/riscv-test-suite/rv32i/src/I-EBREAK-01.S
+++ b/riscv-test-suite/rv32i/src/I-EBREAK-01.S
@@ -71,6 +71,7 @@ RV_COMPLIANCE_CODE_BEGIN
# ---------------------------------------------------------------------------------------------
# Exception handler
+ .align 2
_trap_handler:
# increment return address
csrr x30, mepc
diff --git a/riscv-test-suite/rv32i/src/I-ECALL-01.S b/riscv-test-suite/rv32i/src/I-ECALL-01.S
index 5278207..d181526 100644
--- a/riscv-test-suite/rv32i/src/I-ECALL-01.S
+++ b/riscv-test-suite/rv32i/src/I-ECALL-01.S
@@ -73,6 +73,7 @@ RV_COMPLIANCE_CODE_BEGIN
# ---------------------------------------------------------------------------------------------
# Exception handler
+ .align 2
_trap_handler:
# increment return address
csrr x30, mepc
diff --git a/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S b/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S
index 8f54534..a09cf76 100644
--- a/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S
+++ b/riscv-test-suite/rv32i/src/I-MISALIGN_JMP-01.S
@@ -277,6 +277,7 @@ RV_COMPLIANCE_CODE_BEGIN
# ---------------------------------------------------------------------------------------------
# Exception handler
+ .align 2
_trap_handler:
# increment return address
csrr x30, mbadaddr
diff --git a/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S b/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S
index 5a20187..0eeb9d1 100644
--- a/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S
+++ b/riscv-test-suite/rv32i/src/I-MISALIGN_LDST-01.S
@@ -188,6 +188,7 @@ RV_COMPLIANCE_CODE_BEGIN
# ---------------------------------------------------------------------------------------------
# Exception handler
+ .align 2
_trap_handler:
# increment return address
csrr x30, mepc