Skip to content

Issues: ucsdsysnet/Rosebud

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

7 Open 0 Closed
7 Open 0 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Cell is placed inside reconfig block
#7 opened Mar 1, 2023 by hoangvm97
1
Compile with normal flow (no partial reconfig) error
#6 opened Mar 1, 2023 by hoangvm97
Add RPU and interface count readbacks to the FPGA image enhancement New feature or request
#5 opened Feb 11, 2023 by mkhazraee
Update PCIe modules to support straddling enhancement New feature or request
#4 opened Nov 23, 2022 by mkhazraee
Testbenches insert packets at higher rate than 100Gbps per interface enhancement New feature or request
#3 opened Nov 15, 2022 by mkhazraee
Very rarely a slot is returned to the LB which was supposed to be in LB and not the RPUs. bug Something isn't working enhancement New feature or request
#2 opened Nov 15, 2022 by mkhazraee
1
Adjust when to drop packets per incoming interface for the RR scheduler bug Something isn't working enhancement New feature or request
#1 opened Nov 15, 2022 by mkhazraee
1
ProTip! Type g p on any issue or pull request to go back to the pull request listing page.