[RFC] Upgrade to User-level ISA v2.2 and Privileged Architecture v1.10

[liangfu]

Current riscv-mini implements RV32I of the User-level ISA Version 2.0 and the Machine-level ISA of the Privileged Architecture Version 1.7. This requires the users to build and install RISC-V tools for priv 1.7. If we upgrade the implement to user-level ISA to version 2.2 and privileged architecture to version 1.10, users could download latest pre-built compiler from xpack-dev-tools and generate the executable much easier.

Major User-level Base ISA Changes

Changes from v2.1 to v2.2

• Rearranged chapters to put all extensions first in canonical order.
• Improvements to the description and commentary.
• Modified implicit hinting suggestion on JALR to support more efficient macro-op fusion of
  LUI/JALR and AUIPC/JALR pairs.
• Clarification of constraints on load-reserved/store-conditional sequences.
• A new table of control and status register (CSR) mappings.
• Clarified purpose and behavior of high-order bits of fcsr.
• Specified behavior of narrower (<FLEN) floating-point values held in wider f registers using
  NaN-boxing model.
• Defined the exception behavior of FMA(∞, 0, qNaN).

Changes from v2.0 to v2.1

• Modification to long instruction encodings >64 bits to avoid moving the rd specifier in very
  long instruction formats.
• CSR instructions are now described in the base integer format where the counter registers
  are introduced, as opposed to only being introduced later in the floating-point section (and
  the companion privileged architecture manual).
• The SCALL and SBREAK instructions have been renamed to ECALL and EBREAK, re-
  spectively. Their encoding and functionality are unchanged.
• Clarification of LR/SC allowed successes and required failures, including use of compressed
  instructions in the sequence.

Major Privileged Architecture Changes

Changes from v1.9.1 to v1.10

• The explicit convention on shadow CSR addresses has been removed to reclaim CSR space.
  Shadow CSRs can still be added as needed.
• The mvendorid register now contains the JEDEC code of the core provider as opposed to
  a code supplied by the Foundation. This avoids redundancy and offloads work from the
  Foundation.
• The interrupt-enable stack discipline has been simplified.
• An optional mechanism to change the base ISA used by supervisor and user modes has been
  added to the mstatus CSR, and the field previously called Base in misa has been renamed
  to MXL for consistency.
• Clarified expected use of XS to summarize additional extension state status fields in mstatus.
• Optional vectored interrupt support has been added to the mtvec and stvec CSRs.
• The SEIP and UEIP bits in the mip CSR have been redefined to support software injection
  of external interrupts.
• The mbadaddr register has been subsumed by a more general mtval register that can now
  capture bad instruction bits on an illegal instruction fault to speed instruction emulation.
• The machine-mode base-and-bounds translation and protection schemes have been removed
  from the specification as part of moving the virtual memory configuration to sptbr (now
  satp). Some of the motivation for the base and bound schemes are now covered by the PMP
  registers, but space remains available in mstatus to add these back at a later date if deemed
  useful.
• In systems with only M-mode, or with both M-mode and U-mode but without U-mode
  trap support, the medeleg and mideleg registers now do not exist, whereas previously they
  returned zero.
• Virtual-memory page faults now have mcause values distinct from physical-memory access
  exceptions. Page-fault exceptions can now be delegated to S-mode without delegating excep-
  tions generated by PMA and PMP checks.
• An optional physical-memory protection (PMP) scheme has been proposed.
• The supervisor virtual memory configuration has been moved from the mstatus register to
  the sptbr register. Accordingly, the sptbr register has been renamed to satp (Supervisor Address Translation and Protection) to reflect is broadened role.
• The SFENCE.VM instruction has been removed in favor of the improved SFENCE.VMA
  instruction.
• The mstatus bit MXR has been exposed to S-mode via sstatus.
• The polarity of the PUM bit in sstatus has been inverted to shorten code sequences involving
  MXR. The bit has been renamed to SUM.
  Hardware management of page-table entry Accessed and Dirty bits has been made optional;
  simpler implementations may trap to software to set them.
• The counter-enable scheme has changed, so that S-mode can control availability of counters
  to U-mode.
• H-mode has been removed, as we are focusing on recursive virtualization support in S-mode.
• The encoding space has been reserved and may be repurposed at a later date.
• A mechanism to improve virtualization performance by trapping S-mode virtual-memory
  management operations has been added.
• The Supervisor Binary Interface (SBI) chapter has been removed, so that it can be maintained
  as a separate specification.

Changes from v1.9 to v1.9.1

• Numerous additions and improvements to the commentary sections.
• Change configuration string proposal to be use a search process that supports various formats
  including Device Tree String and flattened Device Tree.
• Made misa optionally writable to support modifying base and supported ISA extensions.
  CSR address of misa changed.
• Added description of debug mode and debug CSRs.
• Added a hardware performance monitoring scheme. Simplified the handling of existing hard-
  ware counters, removing privileged versions of the counters and the corresponding delta reg-
  isters.
• Fixed description of SPIE in presence of user-level interrupts.

Changes from v1.7 to v1.9

(Not yet available.)

For more details, please refer to the documents here.

Please leave your comments.

[ekiwi]

@vighneshiyer is now working on this

[ObiWanRohan]

The ERET instruction has been updated to the MRET,SRET and URET instructions.
The riscv-mini core is still using the old ERET instruction.