diff --git a/Makefile b/Makefile index 34d0e7843..bdc8e7746 100644 --- a/Makefile +++ b/Makefile @@ -4,7 +4,7 @@ base_dir = $(abspath .) src_dir = $(base_dir)/src/main gen_dir = $(base_dir)/generated-src out_dir = $(base_dir)/outputs -nproc = $(shell nproc --ignore 1) +threads ?= 1 SBT = sbt SBT_FLAGS = -ivy $(base_dir)/.ivy2 @@ -17,11 +17,11 @@ compile: $(gen_dir)/Tile.sv $(gen_dir)/Tile.sv: $(wildcard $(src_dir)/scala/*.scala) $(SBT) $(SBT_FLAGS) "run --target-dir=$(gen_dir)" -CXXFLAGS += -std=c++11 -Wall -Wno-unused-variable +CXXFLAGS += -std=c++14 -Wall -Wno-unused-variable # compile verilator VERILATOR = verilator --cc --exe -VERILATOR_FLAGS = --assert -Wno-STMTDLY -O3 --trace --threads $(nproc)\ +VERILATOR_FLAGS = --assert -Wno-STMTDLY -O3 --trace --threads $(threads)\ --top-module Tile -Mdir $(gen_dir)/VTile.csrc \ -CFLAGS "$(CXXFLAGS) -include $(gen_dir)/VTile.csrc/VTile.h" diff --git a/build.sbt b/build.sbt index b82b3f18e..a70f22b58 100644 --- a/build.sbt +++ b/build.sbt @@ -2,8 +2,8 @@ ThisBuild / scalaVersion := "2.13.7" ThisBuild / version := "2.5.0" ThisBuild / organization := "edu.berkeley.cs" -val chiselVersion = "5.0.0" -val chiseltestVersion = "5.0.2" +val chiselVersion = "6.2.0" +val chiseltestVersion = "6.0.0" lazy val root = (project in file(".")) .settings( diff --git a/src/main/scala/mini/CSR.scala b/src/main/scala/mini/CSR.scala index f7c56aecd..a55a97ec7 100644 --- a/src/main/scala/mini/CSR.scala +++ b/src/main/scala/mini/CSR.scala @@ -159,7 +159,7 @@ class CSR(val xlen: Int) extends Module { val FS = 0.U(2.W) val SD = 0.U(1.W) val mstatus = Cat(SD, 0.U((xlen - 23).W), VM, MPRV, XS, FS, PRV3, IE3, PRV2, IE2, PRV1, IE1, PRV, IE) - val mtvec = Const.PC_EVEC.U(xlen.W) + val mtvec = Consts.PC_EVEC.U(xlen.W) val mtdeleg = 0x0.U(xlen.W) // interrupt registers diff --git a/src/main/scala/mini/Datapath.scala b/src/main/scala/mini/Datapath.scala index 4d55de731..cf2c4e511 100644 --- a/src/main/scala/mini/Datapath.scala +++ b/src/main/scala/mini/Datapath.scala @@ -6,7 +6,7 @@ import chisel3._ import chisel3.util._ import chisel3.experimental.BundleLiterals._ -object Const { +object Consts { val PC_START = 0x200 val PC_EVEC = 0x100 } @@ -76,7 +76,7 @@ class Datapath(val conf: CoreConfig) extends Module { */ val started = RegNext(reset.asBool) val stall = !io.icache.resp.valid || !io.dcache.resp.valid - val pc = RegInit(Const.PC_START.U(conf.xlen.W) - 4.U(conf.xlen.W)) + val pc = RegInit(Consts.PC_START.U(conf.xlen.W) - 4.U(conf.xlen.W)) // Next Program Counter val next_pc = MuxCase( pc + 4.U, diff --git a/src/test/scala/mini/CSRTests.scala b/src/test/scala/mini/CSRTests.scala index 31315a17c..3437383dc 100644 --- a/src/test/scala/mini/CSRTests.scala +++ b/src/test/scala/mini/CSRTests.scala @@ -65,7 +65,7 @@ class CSRTester(c: => CSR, trace: Boolean = false) extends BasicTester with Test addr -> RegInit( if (addr == CSR.mcpuid.litValue) (BigInt(1) << ('I' - 'A') | BigInt(1) << ('U' - 'A')).U(xlen.W) else if (addr == CSR.mstatus.litValue) (CSR.PRV_M.litValue << 4 | CSR.PRV_M.litValue << 1).U(xlen.W) - else if (addr == CSR.mtvec.litValue) Const.PC_EVEC.U(xlen.W) + else if (addr == CSR.mtvec.litValue) Consts.PC_EVEC.U(xlen.W) else 0.U(xlen.W) ) } diff --git a/src/test/scala/mini/DatapathTests.scala b/src/test/scala/mini/DatapathTests.scala index 139dfb8cf..38ac12ced 100644 --- a/src/test/scala/mini/DatapathTests.scala +++ b/src/test/scala/mini/DatapathTests.scala @@ -42,10 +42,10 @@ class DatapathTester(datapath: => Datapath, testType: DatapathTest) extends Basi switch(state) { is(sInit) { - (0 until Const.PC_START by 4).foreach { addr => - mem((addr / 4).U) := (if (addr == Const.PC_EVEC + (3 << 6)) fin else nop) + (0 until Consts.PC_START by 4).foreach { addr => + mem((addr / 4).U) := (if (addr == Consts.PC_EVEC + (3 << 6)) fin else nop) } - mem((Const.PC_START / (xlen / 8)).U + cntr) := VecInit(insts)(cntr) + mem((Consts.PC_START / (xlen / 8)).U + cntr) := VecInit(insts)(cntr) when(done) { state := sRun } } is(sRun) {