diff --git a/FPGA/SSMaster.v b/FPGA/SSMaster.v index 5cb85e6..1fe2ae7 100644 --- a/FPGA/SSMaster.v +++ b/FPGA/SSMaster.v @@ -5,6 +5,10 @@ // version 0.1: first step. // 0.2: for HW1.2 +// 0.3: +// 0.4: support put_sector_data +// 0.5: CDC bug fix + module SSMaster( // System @@ -227,9 +231,10 @@ module SSMaster( if(NRESET==0) begin st_reg_ctrl <= 0; st_reg_spi <= 3'b111; + st_reg_sdram <= 12'b11_1100001101; // type:64MB refcnt: 0x30d(7.81us) end else if(st_wr_start==1) begin if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h04) st_reg_ctrl <= ST_AD; - if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h16) st_reg_spi <= ST_AD[3:1]; + if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h16) {st_reg_sdram, st_reg_spi} <= ST_AD[15:1]; if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h20) ss_resp1 <= ST_AD; if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h22) ss_resp2 <= ST_AD; if(fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h24) ss_resp3 <= ST_AD; @@ -369,16 +374,17 @@ module SSMaster( begin st_reg_data_out <= (fsmc_addr[7:0]==8'h00)? 16'h5253 : // ID: "SR" - (fsmc_addr[7:0]==8'h02)? 16'h1204 : // ver: HW1.2 && SW0.4 + (fsmc_addr[7:0]==8'h02)? 16'h1205 : // ver: HW1.2 && SW0.5 (fsmc_addr[7:0]==8'h04)? st_reg_ctrl : (fsmc_addr[7:0]==8'h06)? st_reg_stat : (fsmc_addr[7:0]==8'h08)? st_fifo_data_out : (fsmc_addr[7:0]==8'h0a)? st_fifo_data_out : (fsmc_addr[7:0]==8'h0c)? st_fifo_stat : + (fsmc_addr[7:0]==8'h0e)? st_fifo_rcnt : (fsmc_addr[7:0]==8'h10)? ss_reg_cmd : (fsmc_addr[7:0]==8'h12)? ss_reg_data : (fsmc_addr[7:0]==8'h14)? ss_reg_ctrl : - (fsmc_addr[7:0]==8'h16)? {12'b0, EPCS_CS, EPCS_CLK, EPCS_DI, EPCS_DO} : + (fsmc_addr[7:0]==8'h16)? {st_reg_sdram, EPCS_CS, EPCS_CLK, EPCS_DI, EPCS_DO} : (fsmc_addr[7:0]==8'h18)? ss_resp1 : (fsmc_addr[7:0]==8'h1a)? ss_resp2 : @@ -440,7 +446,7 @@ module SSMaster( always @(posedge mclk) begin - sscs_s0 <= (SS_CS0 & SS_CS1 & SS_CS2); + sscs_s0 <= (SS_CS0 & SS_CS1 & SS_CS2) | ~SS_FC1; sscs_s1 <= sscs_s0; sscs_s2 <= sscs_s1; sscs_s3 <= sscs_s2; @@ -463,7 +469,7 @@ module SSMaster( (SS_RD==0 && ss_cdc_cs==1)? ss_cdc_data_out : 16'hzzzz; - assign SS_DATA_OE = (SS_CS0==1 && SS_CS1==1 && (SS_CS2==1 || (ss_cdc_cs==1 && SS_RD==0 && ss_cdc_en==0))); + assign SS_DATA_OE = ~SS_FC1 | (SS_CS0==1 && SS_CS1==1 && (SS_CS2==1 || (ss_cdc_cs==1 && SS_RD==0 && ss_cdc_en==0))); assign SS_DATA_DIR = (SS_WR0 & SS_WR1); @@ -497,7 +503,7 @@ module SSMaster( begin ss_bcr_data_out <= (SS_ADDR[5:1]==5'b00_000)? 16'h5253 : // ID: "SR" - (SS_ADDR[5:1]==5'b00_001)? 16'h1204 : // ver: HW1.2 && SW0.4 + (SS_ADDR[5:1]==5'b00_001)? 16'h1205 : // ver: HW1.2 && SW0.5 (SS_ADDR[5:2]==4'b00_01 )? ss_reg_ctrl : (SS_ADDR[5:2]==4'b00_10 )? ss_reg_stat : (SS_ADDR[5:1]==5'b00_110)? ss_reg_timer[31:16] : @@ -594,6 +600,19 @@ module SSMaster( .full(fifo_full) ); + // Saturn set and STM32 reset + reg[15:0] st_fifo_rcnt; + always @(negedge NRESET or posedge mclk) + begin + if(NRESET==0) + st_fifo_rcnt <= 4'b0000; + else if(st_wr_start==1 && fsmc_addr[24]==0 && fsmc_addr[7:0]==8'h0e) + st_fifo_rcnt <= 0; + else if(ss_fifo_read) + st_fifo_rcnt <= st_fifo_rcnt+1'b1; + end + + /////////////////////////////////////////////////////// // SATURN CDC // /////////////////////////////////////////////////////// @@ -649,7 +668,8 @@ module SSMaster( // SDRAM // /////////////////////////////////////////////////////// - + reg[11:0] st_reg_sdram; + // STM32 is LittleEndian system wire[25:0] st_ram_addr = {2'b0, fsmc_addr[23:0]}; wire[ 1:0] st_mask = {ST_BL1,ST_BL0}; @@ -689,7 +709,7 @@ module SSMaster( NRESET, mclk, ss_ram_cs, ss_rd_start, ss_wr_start, ss_mask, ss_ram_wait, ss_ram_addr, ss_ram_din, ss_ram_dout, st_ram_cs, st_rd_start, st_wr_start, st_mask, st_ram_wait, st_ram_addr, ST_AD, st_ram_data_out, - SD_CKE, SD_CS, SD_RAS, SD_CAS, SD_WE, SD_ADDR, SD_BA, SD_DQM, SD_DQ, ss_refresh + SD_CKE, SD_CS, SD_RAS, SD_CAS, SD_WE, SD_ADDR, SD_BA, SD_DQM, SD_DQ, ss_refresh, st_reg_sdram ); assign SD_CLK = sdclk; diff --git a/FPGA/memhub.v b/FPGA/memhub.v index a2f97d5..6b2a51c 100644 --- a/FPGA/memhub.v +++ b/FPGA/memhub.v @@ -8,7 +8,7 @@ module memhub( cs_a, rd_a, wr_a, mask_a, nwait_a, addr_a, wdata_a, rdata_a, cs_b, rd_b, wr_b, mask_b, nwait_b, addr_b, wdata_b, rdata_b, sd_cke, sd_cs, sd_ras, sd_cas, sd_we, sd_addr, sd_ba, sd_dqm, sd_data, - ext_refresh + ext_refresh, reg_sdram ); /////////////////////////////////////////////////////// @@ -50,6 +50,7 @@ module memhub( output[ 1:0] sd_dqm; inout [15:0] sd_data; input ext_refresh; + input [11:0] reg_sdram; /////////////////////////////////////////////////////// @@ -186,7 +187,7 @@ module memhub( wire sd_oe; tsdram _tsd( - reset, clk, + reset, clk, reg_sdram, ext_refresh, cmd_req, cmd_ack, cmd_mask, cmd_addr, cmd_din, cmd_dout, data_valid, sd_cke, sd_cs, sd_ras, sd_cas, sd_we, sd_addr, sd_ba, sd_dqm, sd_data, sd_dout, sd_oe ); diff --git a/FPGA/tsdram.v b/FPGA/tsdram.v index 3579e1c..3f9a3c0 100644 --- a/FPGA/tsdram.v +++ b/FPGA/tsdram.v @@ -6,6 +6,7 @@ module tsdram( reset, clk, + reg_sdram, ext_refresh, cmd_req, @@ -37,6 +38,7 @@ module tsdram( input reset; input clk; + input [11:0] reg_sdram; input ext_refresh; input [ 1:0] cmd_req; @@ -87,15 +89,40 @@ module tsdram( /////////////////////////////////////////////////////// // A31 - A26 [A25 - A13] [A12 A11] [A10 - A1] A0 - // [R12 - R0] [ B1 B0] [ C9 - C0] + // [R12 - R0] [ B1 B0] [ C9 - C0] 64MB + // + // A31 - A25 [A24 - A12] [A11 A10] [ A9 - A1] A0 + // [R12 - R0] [ B1 B0] [ C8 - C0] 32MB + // + // A31 - A24 [A23 - A12] [A11 A10] [ A9 - A1] A0 + // [R11 - R0] [ B1 B0] [ C8 - C0] 16MB + // + // A31 - A23 [A22 - A11] [A10 A9] [ A8 - A1] A0 + // [R11 - R0] [ B1 B0] [ C7 - C0] 8MB localparam BANK_POS = COL_BITS+1; localparam ROW_POS = BANK_POS+2; - wire[ROW_BITS-1:0] col_addr = {3'b001, {(10-COL_BITS){1'b0}}, cmd_addr[COL_BITS:1]}; - - wire[1:0] bank_addr = cmd_addr[COL_BITS+2:COL_BITS+1]; - wire[ROW_BITS-1:0] row_addr = cmd_addr[ROW_BITS+COL_BITS+2:COL_BITS+3]; +// wire[ROW_BITS-1:0] col_addr = {3'b001, {(10-COL_BITS){1'b0}}, cmd_addr[COL_BITS:1]}; +// wire[1:0] bank_addr = cmd_addr[COL_BITS+2:COL_BITS+1]; +// wire[ROW_BITS-1:0] row_addr = cmd_addr[ROW_BITS+COL_BITS+2:COL_BITS+3]; + + wire[1:0] sdtype = reg_sdram[11:10]; + wire[12:0] col_addr = + (sdtype==2'b11)? {3'b001, cmd_addr[10:1]} : + (sdtype==2'b10)? {4'b0010, cmd_addr[ 9:1]} : + (sdtype==2'b01)? {4'b0010, cmd_addr[ 9:1]} : + {5'b00100, cmd_addr[ 8:1]} ; + wire[1:0] bank_addr = + (sdtype==2'b11)? cmd_addr[12:11] : + (sdtype==2'b10)? cmd_addr[11:10] : + (sdtype==2'b01)? cmd_addr[11:10] : + cmd_addr[10: 9] ; + wire[12:0] row_addr = + (sdtype==2'b11)? cmd_addr[25:13] : + (sdtype==2'b10)? cmd_addr[24:12] : + (sdtype==2'b01)? {1'b0, cmd_addr[23:12]} : + {1'b0, cmd_addr[22:11]} ; /////////////////////////////////////////////////////// @@ -110,7 +137,8 @@ module tsdram( if(reset==0) begin ref_count <= tPOR_count[15:0]; end else if(ref_ack) begin - ref_count <= tREF_count[15:0]; +// ref_count <= tREF_count[15:0]; + ref_count <= {6'b0, reg_sdram[9:0]}; end else if(ref_count) begin ref_count <= ref_count-1'b1; end diff --git a/Firm_MCU/Main/main.c b/Firm_MCU/Main/main.c index f22623e..53ae0ae 100644 --- a/Firm_MCU/Main/main.c +++ b/Firm_MCU/Main/main.c @@ -244,25 +244,53 @@ int flash_update(int check) _puts("erase ...\n"); retv = flash_erase(firm_addr); if(retv){ - restore_irq(key); - _puts(" faile!\n"); - return -2; + retv = -2; + goto _exit; } _puts("write ...\n"); for(i=0; i=1){ + type = arg[0]; + } + if(argc>=2){ + reftime = arg[1]; + } + sdram_config(type, reftime); + } CMD(mmt){ u32 addr = 0x61000000; @@ -378,6 +389,10 @@ void simple_shell(void) printk("create exram.bin failed! %d\n", retv); } } + CMD(pt){ + void show_pt(int id); + show_pt(arg[0]); + } CMD(q){ break; diff --git a/Firm_MCU/Main/spi1_fpga.c b/Firm_MCU/Main/spi1_fpga.c index 9fbf762..d65f575 100644 --- a/Firm_MCU/Main/spi1_fpga.c +++ b/Firm_MCU/Main/spi1_fpga.c @@ -24,7 +24,7 @@ void fspi_setcs(int val) if(val) ctrl |= 0x08; else - ctrl &= 0x07; + ctrl &= ~0x08; *(volatile u16*)(0x60000016) = ctrl; } @@ -34,7 +34,7 @@ void fspi_setclk(int val) if(val) ctrl |= 0x04; else - ctrl &= 0x0b; + ctrl &= ~0x04; *(volatile u16*)(0x60000016) = ctrl; } @@ -44,7 +44,7 @@ void fspi_setdi(int val) if(val) ctrl |= 0x02; else - ctrl &= 0x0d; + ctrl &= ~0x02; *(volatile u16*)(0x60000016) = ctrl; } @@ -124,6 +124,25 @@ int epcs_status(void) return status; } +int epcs_wstat(int stat) +{ + // status write enable + fspi_setcs(0); + fspi_delay(); + fspi_trans(0x50); + fspi_setcs(1); + fspi_delay(); + + fspi_setcs(0); + fspi_delay(); + fspi_trans(0x01); + fspi_trans(stat); + fspi_setcs(1); + fspi_delay(); + + return 0; +} + int epcs_wen(int en) { fspi_setcs(0); @@ -173,7 +192,7 @@ int epcs_sector_erase(int addr) return 0; } -int epcs_page_write(int addr, u8 *buf) +int epcs_page_write(int addr, u8 *buf, int size) { int i; @@ -187,7 +206,7 @@ int epcs_page_write(int addr, u8 *buf) fspi_trans((addr>> 8)&0xff); fspi_trans((addr>> 0)&0xff); - for(i=0; i<256; i++){ + for(i=0; i>10)&3; + rcnt = (cfgbuf[1])&0x3ff; + printk("SDRAM type: %d refcnt: %d\n", type, rcnt); + + int ctrl = *(volatile u16*)(0x60000016); + ctrl &= 0x000f; + ctrl |= (type<<14) | (rcnt<<4); + *(volatile u16*)(0x60000016) = ctrl; +} + + +/******************************************************************************/ + + int fpga_config_done(void) { return (GPIOB->IDR&0x0800)? 1 : 0; @@ -342,6 +423,8 @@ void fpga_config(void) printk(" status: %d\n", fpga_status()); printk("\n"); + sdram_set(); + return; } diff --git a/Firm_MCU/Main/uart4.c b/Firm_MCU/Main/uart4.c index 9233b55..7f2de6a 100644 --- a/Firm_MCU/Main/uart4.c +++ b/Firm_MCU/Main/uart4.c @@ -218,6 +218,7 @@ void uart4_init(void) UART4->BRR = 0x0; // Reset // UART4->BRR = 0x0364; // 设置波特比率寄存器为115200(100M/115200) UART4->BRR = 0x0064; // 设置波特比率寄存器为1M(100M/1M) +// UART4->BRR = 0x0032; // 设置波特比率寄存器为2M(100M/2M) UART4->RQR = 0x0018; UART4->CR1 |= 0x0001; // Enable UART4 diff --git a/Firm_MCU/Saturn/cdc.h b/Firm_MCU/Saturn/cdc.h index 2a1b429..47811c7 100644 --- a/Firm_MCU/Saturn/cdc.h +++ b/Firm_MCU/Saturn/cdc.h @@ -23,6 +23,7 @@ #define ST_STAT REG16(FPGA_BASE+0x06) #define FIFO_DATA REG16(FPGA_BASE+0x08) #define FIFO_STAT REG16(FPGA_BASE+0x0c) +#define FIFO_RCNT REG16(FPGA_BASE+0x0e) #define SS_CMD REG16(FPGA_BASE+0x10) #define SS_ARG REG16(FPGA_BASE+0x12) #define SS_CTRL REG16(FPGA_BASE+0x14) diff --git a/Firm_MCU/Saturn/saturn_cdc.c b/Firm_MCU/Saturn/saturn_cdc.c index 82f9a22..d6bf91a 100644 --- a/Firm_MCU/Saturn/saturn_cdc.c +++ b/Firm_MCU/Saturn/saturn_cdc.c @@ -176,6 +176,7 @@ void trans_start(void) cdb.trans_size = 24; } + FIFO_RCNT = 0; ST_CTRL &= ~0x0200; fill_fifo(dp, cdb.trans_size); ST_STAT = STIRQ_DAT; @@ -216,17 +217,16 @@ void trans_handle(void) ST_CTRL &= ~STIRQ_DAT; //printk("trans_put: FIFO_STAT=%04x\n", FIFO_STAT); int cnt = 2048; + int offs = 0; + if(cdb.put_sector_size==2048){ + offs = 24; + }else if(cdb.put_sector_size==2336){ + offs = 16; + }else if(cdb.put_sector_size==2340){ + offs= 12; + } while(cnt){ - if(bt->size==0){ - if(cdb.put_sector_size==2048){ - bt->size = 24; - }else if(cdb.put_sector_size==2336){ - bt->size = 16; - }else if(cdb.put_sector_size==2340){ - bt->size = 12; - } - } - *(u16*)(bt->data + bt->size) = FIFO_DATA; + *(u16*)(bt->data + offs + bt->size) = FIFO_DATA; bt->size += 2; cnt -= 2; if(bt->size == cdb.put_sector_size){ @@ -300,6 +300,7 @@ void trans_handle(void) HIRQ = HIRQ_SCDQ; } }else{ + cdb.trans_finish = 1; ST_CTRL &= ~STIRQ_DAT; } } @@ -450,11 +451,15 @@ int filter_sector(TRACK_INFO *track, BLOCK *wblk) // 鏅氬懡浠 +static int old_status; // 0x00 [SR] int get_cd_status(void) { set_report(cdb.status); - SSLOG(_DEBUG, " %02x\n", cdb.status); + if(old_status!=cdb.status){ + SSLOG(_DEBUG, " %02x\n", cdb.status); + old_status = cdb.status; + } return 0; } @@ -478,7 +483,7 @@ int get_toc_info(void) SSLOG(_INFO, "get_toc_info\n"); if(cdb.trans_type){ - set_status(STAT_WAIT); + set_status(STAT_WAIT | cdb.status); return 0; } @@ -599,7 +604,7 @@ int end_trans(void) } } }else{ - SSLOG(_BUFIO, "end_trans: cdwnum=%08x FIFO_STAT=%08x min_num=%d\n", cdb.cdwnum, FIFO_STAT, min_num); + SSLOG(_BUFIO, "end_trans: cdwnum=%08x FIFO_STAT=%08x RCNT=%04x min_num=%d\n", cdb.cdwnum, FIFO_STAT, FIFO_RCNT, min_num); fifo_remain = (FIFO_STAT&0x0fff)*2; // FIFO涓繕鏈夊灏戝瓧鑺傛湭璇 if(fifo_remain>=512){ //FIFO涓殑鏁版嵁澶т簬512瀛楄妭锛屼笉浼氫骇鐢熶腑鏂俢dwnum浼氬皯璁颁竴娆° @@ -667,6 +672,7 @@ int play_cd(void) HIRQ_CLR = HIRQ_PEND; + int play_tno = 0; if(start_pos==0xffffff){ // PTYPE_NOCHG }else if(start_pos&0x800000){ @@ -681,7 +687,7 @@ int play_cd(void) cdb.play_fad_start = track_to_fad(start_pos); cdb.track = (start_pos>>8)&0xff; cdb.index = start_pos&0xff; - mode &= 0x7f; + play_tno = 1; } if(end_pos==0xffffff){ @@ -695,6 +701,11 @@ int play_cd(void) cdb.play_fad_end = track_to_fad(end_pos); else cdb.play_fad_end = track_to_fad((end_pos&0xff00)|0x63); + if(play_tno){ + // STEAM-HEART'S fixup + // 鏄庣‘鎸囧畾start涓巗top鐨勬儏鍐典笅,寮哄埗鏇存柊fad. + cdb.fad = cdb.play_fad_start; + } }else{ // PTYPE_DFL cdb.play_fad_end = track_to_fad(0xffff); @@ -744,6 +755,10 @@ int seek_cd(void) cdb.index = 1; cdb.options = 0x00; cdb.repcnt = 0; + // 涓夊浗蹇: 鍚為澶╁湴2 + // Seek鍚, Play(00ffffff, 00ffffff, ff). + // 闇瑕佹寚瀹歱lay_fad_end浠ュ厤Play澶氳鏁版嵁. + cdb.play_fad_end = 0; }else{ // PTYPE_TNO if(pos){ @@ -800,7 +815,7 @@ int get_subcode(void) int rel_fad, rm, rs, rf, m, s, f; if(cdb.trans_type){ - set_status(STAT_WAIT); + set_status(STAT_WAIT | cdb.status); return 0; } @@ -1243,7 +1258,7 @@ int get_sector_data(void) PARTITION *pp; if(cdb.trans_type){ - set_status(STAT_WAIT); + set_status(STAT_WAIT | cdb.status); return 0; } @@ -1260,18 +1275,20 @@ int get_sector_data(void) snum = pp->numblocks-spos; } SSLOG(_BUFIO, "get_sector_data: part=%d(%d) spos=%d snum=%d\n", pt, pp->numblocks, spos, snum); + if(spos<0 || snum<=0 || (spos+snum) > pp->numblocks){ + set_status(STAT_WAIT | cdb.status); + return 0; + } gs_spos = spos; gs_snum = snum; - if(pp->numblocks){ - cdb.trans_type = TRANS_DATA; - cdb.trans_part_index = pt; - cdb.trans_block_start = spos; - cdb.trans_block_end = spos+snum; + cdb.trans_type = TRANS_DATA; + cdb.trans_part_index = pt; + cdb.trans_block_start = spos; + cdb.trans_block_end = spos+snum; + trans_start(); - trans_start(); - } - set_status(0x4000 | cdb.status); + set_status(STAT_TRNS | cdb.status); return HIRQ_DRDY|HIRQ_EHST; } @@ -1293,14 +1310,15 @@ int del_sector_data(void) if(spos==0xffff){ spos = pp->numblocks-1; } - if(spos>=pp->numblocks){ - // 姊﹀够涔嬫槦1浼氫紶鍏pos=180瀵艰嚧鍚庣画閿欒 - spos = 0; - } if(snum==0xffff){ snum = pp->numblocks-spos; } SSLOG(_BUFIO, "del_sector_data: part=%d spos=%d snum=%d\n", pt, spos, snum); + if(spos<0 || snum<=0 || (spos+snum) > pp->numblocks){ + // 姊﹀够涔嬫槦1浼氫紶鍏pos=180瀵艰嚧鍚庣画閿欒 + set_status(STAT_WAIT | cdb.status); + return 0; + } while(snum){ remove_block(pp, spos); @@ -1319,7 +1337,7 @@ int get_del_sector_data(void) gs_snum = 0; if(cdb.trans_type){ - set_status(STAT_WAIT); + set_status(STAT_WAIT | cdb.status); return 0; } @@ -1328,47 +1346,27 @@ int get_del_sector_data(void) snum = cdb.cr4; pp = &cdb.part[pt]; - if(pp->numblocks){ - if(spos==0xffff){ - spos = pp->numblocks-1; - } - if(snum==0xffff){ - snum = pp->numblocks-spos; - } - }else{ - if(spos==0xffff){ - spos = 0; - } - if(snum==0xffff){ - snum = 0; - } - } - SSLOG(_BUFIO, "get_del_sector_data: part=%d(%d) spos=%d snum=%d\n", pt, pp->numblocks, spos, snum); - if(snum==0){ - // 閽堝<閲嶈鏈哄叺2闆疯鏂>鐨勪复鏃跺鐞 - while(cdb.play_type){ - cdc_delay(10); - } - snum = pp->numblocks; - }else{ - while(pp->numblocksnumblocks-1; + } + if(snum==0xffff){ + snum = pp->numblocks-spos; } SSLOG(_BUFIO, " : part=%d(%d) spos=%d snum=%d\n", pt, pp->numblocks, spos, snum); - - if(pp->numblocks){ - cdb.trans_type = TRANS_DATA_DEL; - cdb.trans_part_index = pt; - cdb.trans_block_start = spos; - cdb.trans_block_end = spos+snum; - - trans_start(); + if(spos<0 || snum<=0 || (spos+snum) > pp->numblocks){ + // 鏍煎叞钂備簹: 浼犲叆浜唖num=0. 浼间箮搴旇鐩存帴杩斿洖. + set_status(STAT_WAIT | cdb.status); + return 0; } - set_status(0x4000 | cdb.status); + cdb.trans_type = TRANS_DATA_DEL; + cdb.trans_part_index = pt; + cdb.trans_block_start = spos; + cdb.trans_block_end = spos+snum; + trans_start(); + + set_status(STAT_TRNS | cdb.status); return HIRQ_DRDY|HIRQ_EHST; } @@ -1380,7 +1378,7 @@ int put_sector_data(void) PARTITION *pp; if(cdb.trans_type){ - set_status(STAT_WAIT); + set_status(STAT_WAIT | cdb.status); return 0; } @@ -1525,9 +1523,9 @@ int handle_diread(void) SSLOG(_FILEIO, " cdir_lba=%08x size=%08x\n", cdb.cdir_lba, cdb.cdir_size); fill_fileinfo(); free_partition(pt); + HIRQ = HIRQ_EFLS; } - HIRQ = HIRQ_EFLS; return 0; } @@ -1661,7 +1659,7 @@ int get_file_info(void) int i; if(cdb.trans_type){ - set_status(STAT_WAIT); + set_status(STAT_WAIT | cdb.status); return 0; } @@ -1760,10 +1758,11 @@ int read_file(void) _set_filter(selnum, 0x40, cdb.play_fad_start, lba_size-offset); disk_task_wakeup(); - set_report(0x4000 | cdb.status); - return HIRQ_EFLS; + set_report(cdb.status); + return 0; } + // 0x75 [SR] int abort_file(void) { diff --git a/Firm_MCU/Saturn/saturn_main.c b/Firm_MCU/Saturn/saturn_main.c index af87dd5..dc5f32e 100644 --- a/Firm_MCU/Saturn/saturn_main.c +++ b/Firm_MCU/Saturn/saturn_main.c @@ -153,6 +153,8 @@ int get_sector(int fad, BLOCK *wblk) return -1; } } + if(wblk==NULL) + return 0; if(fad>=buf_fad_start && fadnumblocks); + bk = pt->head; + for(i=0; inumblocks; i++){ + SSLOG(_INFO, " %2d: size=%4d fad=%08x data=%08x\n", i, bk->size, bk->fad, bk->data); + bk = bk->next; } - ft = &cdb.filter[cdb.cddev_filter]; - pt = &cdb.part[ft->c_true]; - - SSLOG(_INFO, " : Part_%d: nblks=%d\n", ft->c_true, pt->numblocks); - - } @@ -281,6 +282,9 @@ void disk_task(void *arg) set_pause_ok(); goto _restart_wait; } + + get_sector(cdb.fad, NULL); + if(cdb.play_fad_start==0 || cdb.play_type==0){ SSLOG(_DTASK, "play_task: play_type=%d! play_fad_start=%08x!\n", cdb.play_type, cdb.play_fad_start); cdb.status = STAT_PAUSE; @@ -291,8 +295,9 @@ void disk_task(void *arg) }else{ SSLOG(_DTASK, "\nplay_task! fad_start=%08x(lba_%d) fad_end=%08x fad=%08x type=%d free=%d\n", cdb.play_fad_start, cdb.play_fad_start-150, cdb.play_fad_end, cdb.fad, cdb.play_type, cdb.block_free); - if(cdb.play_fad_start == cdb.fad){ + if(cdb.play_type==PLAYTYPE_SECTOR && cdb.play_fad_start == cdb.fad){ if(play_delay){ + cdb.status = STAT_SEEK; hw_delay(play_delay); } } @@ -329,7 +334,7 @@ void disk_task(void *arg) }else { //printk("filter sector %08x...\n", cdb.fad); - if(sector_delay){ + if(cdb.play_type==PLAYTYPE_SECTOR && sector_delay){ hw_delay(sector_delay); } retv = filter_sector(play_track, &wblk); @@ -341,6 +346,9 @@ void disk_task(void *arg) SSLOG(_DTASK, "buffer full! wait ...\n"); // block缂撳瓨宸叉弧, 闇瑕佺瓑寰呮煇涓簨浠跺啀缁х画 HIRQ = HIRQ_BFUL; + if(cdb.play_type==PLAYTYPE_FILE){ + HIRQ = HIRQ_EFLS; + } cdb.status = STAT_PAUSE; cdb.play_wait = 1; goto _restart_wait; diff --git a/Firm_MCU/inc/main.h b/Firm_MCU/inc/main.h index 1024c9c..f799745 100644 --- a/Firm_MCU/inc/main.h +++ b/Firm_MCU/inc/main.h @@ -62,6 +62,7 @@ void saturn_config(void); int flash_update(int check); int fpga_update(int check); +int flash_write_config(u8 *cfgbuf); /******************************************************************************/ diff --git a/Firm_Saturn/game_patch.c b/Firm_Saturn/game_patch.c index de5caa2..631712e 100644 --- a/Firm_Saturn/game_patch.c +++ b/Firm_Saturn/game_patch.c @@ -165,6 +165,15 @@ void Metal_Slug_patch(void) } +/*********************************************************/ + //Metal_Slug A 合金弹头1.005版 +void Metal_Slug_A_patch(void) +{ + ssctrl_set(MASK_EXMEM, CS0_RAM1M); + *(u32*)(0x06079FBC) = 0x34403440; +} + + /**********************************************************/ // KOF96 // 1MB RAM cart only @@ -331,6 +340,26 @@ void xmvsf_patch(void) } +/**********************************************************/ +// Marvel Super Heroes vs. Street Fighter (Japan) +void mshvssf_handle1(void) +{ + if(*(u16*)(0x600286e)== 0x2012) + *(u16*)(0x600286e) = 0x0009; + if(*(u16*)(0x600205A)== 0x2102) + *(u16*)(0x600205A) = 0x0009; + __asm volatile("jmp @%0"::"r"(0x6002000)); + __asm volatile ("nop" :: ); +} + +void mshvssf_patch(void) +{ + *(u8*)0x060F000B = 0x46; + *(u8*)0x060F001D = 0x41; + *(u32*)(0x60F0124) = (u32)mshvssf_handle1; +} + + /**********************************************************/ // WAKUWAKU7 火热火热7 未修复 void WAKU7_patch(void) @@ -361,7 +390,7 @@ void FIGHTERS_HISTORY_patch(void) { *(u16*)0x060507C4 = 0x9; *(u16*)0x060507d8 = 0x9; - SS_CTRL = (SAROO_EN | CS0_RAM1M); + ssctrl_set(MASK_EXMEM, CS0_RAM1M); *(u32*)0x060500C8 = 0x34403440; *(u32*)0x06057000 = 0x34403440; *(u32*)0x0605707C = 0x34403440; @@ -404,7 +433,8 @@ GAME_DB game_dbs[] = { {"T-1230G", "POCKET_FIGHTER", POCKET_FIGHTER_patch}, {"T-1246G", "SF_ZERO3", SF_ZERO3_patch}, - {"T-3111G", "Metal_Slug", Metal_Slug_patch}, + {"T-3111G V1.002", "Metal_Slug", Metal_Slug_patch}, + {"T-3111G V1.005", "Metal_Slug_A", Metal_Slug_A_patch}, {"T-3108G", "KOF96", kof96_patch}, {"T-3121G", "KOF97", kof97_patch}, {"T-3104G", "SamuraiSp3", smrsp3_patch}, @@ -422,6 +452,7 @@ GAME_DB game_dbs[] = { {"T-1248G", "FINAL_FIGHT_REVENGE", FINAL_FIGHT_REVENGE_patch}, {"T-1226G", "XMENVSSF", xmvsf_patch}, {"T-1215G", "MARVEL_SUPER", MARVEL_SUPER_patch}, + {"T-1238G V1.000", "MSH_VS_SF", mshvssf_patch}, {NULL,}, }; diff --git a/Firm_Saturn/game_save.c b/Firm_Saturn/game_save.c index 3705125..84b399f 100644 --- a/Firm_Saturn/game_save.c +++ b/Firm_Saturn/game_save.c @@ -421,7 +421,7 @@ int bup_dir(int dev, char *file_name, int tbsize, BUPDIR *dir) printk("bup_dir(%d): %s %d\n", dev, file_name, tbsize); if(dev>0) - return BUP_NON; + return 0; fnum = 0; while(1){