From 7dcb91dfb837a9ea854d91bbbd105b76b35822ab Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Tue, 29 Jan 2019 10:37:39 -0800 Subject: [PATCH] documentation for rocket chip as target --- doc/README.adoc | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/doc/README.adoc b/doc/README.adoc index b6bb39e..7dfb196 100644 --- a/doc/README.adoc +++ b/doc/README.adoc @@ -121,6 +121,10 @@ Jeremy Bennett, Mary Bennett, Simon Davidmann, Neel Gala, Radek Hajek, Lee Moore [cols="<1,<2,<3,<4",options="header,pagewidth",] |================================================================================ | _Revision_ | _Date_ | _Author_ | _Modification_ +| 1.13 Draft | 29 January 2019 | +Deborah Soung | + +Added documentation on how to use Rocket Chip generated cores as targets. | 1.12 Draft | 22 November 2018 | Simon Davidmann | @@ -349,6 +353,16 @@ tbd === Berkeley Spike ISA simulator For spike the file `riscv-target/spike/compliance_io.h` has the trace macros defined as empty. The Makefile fragment in `riscv-target/spike/device/rv32i` has the spike run command for the RV32I device. +=== Rocket Chip emulators +Additional environment variables: + +* `ROCKET_DIR`: Specifies link:https://github.com/freechipsproject/rocket-chip[Rocket Chip] directory. Required. +* `ROCKET_CONFIG`: Specifies Rocket Chip link:https://github.com/freechipsproject/rocket-chip/blob/master/src/main/scala/system/Configs.scala[configuration]. **Usually** defaults to `DefaultConfig` or `DefaultRV32Config`, unless the aforementioned configurations do not support a test suite's ISA extensions (for example, in the case of `rv32ud`). + +Before running the compliance test, make sure that the correct emulator is built, following the link:https://github.com/freechipsproject/rocket-chip#emulator[instructions in the Rocket Chip repository]. + +**Note**: Rocket Chip's `DefaultRV32Config` is currently failing the following tests — link:https://github.com/riscv/riscv-compliance/issues/31[rv32i/I-MISALIGN_JMP-01.S], link:https://github.com/riscv/riscv-compliance/issues/32[rv32mi/breakpoint.S], link:https://github.com/riscv/riscv-compliance/issues/33[rv32si/ma_fetch.S]. + === SiFive Freedom Unleashed 540 board (tbd) tbd