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allwinner_a13.lib
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allwinner_a13.lib
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EESchema-LIBRARY Version 2.3 19/03/2013-18:06:13
# Converted with eagle2kicad.ulp Version 0.9
# Device count = 1
#
# Dev Name: OLIMEX_IC_A13
# Package Name: OLIMEX_IC_TQFP176
# Dev Tech: ''
# Dev Prefix: U
# Gate count = 1
#
DEF OLIMEX_IC_A13 U 0 40 Y Y 1 L N
F0 "U" -1400 5430 50 H V L B
F1 "OLIMEX_IC_A13" -1400 -5500 50 H V L B
F2 "allwinner_a13-OLIMEX_IC_TQFP176" 0 150 50 H I C C
DRAW
P 2 1 0 0 1500 -5400 -1500 -5400
P 2 1 0 0 -1500 -5400 -1500 5400
P 2 1 0 0 -1500 5400 1500 5400
P 2 1 0 0 1500 5400 1500 -5400
X AGND 79 -1700 2300 200 R 40 40 1 1 W
X AVCC 81 -1700 2600 200 R 40 40 1 1 W
X DDR3_A0 64 1700 3600 200 L 40 40 1 1 O
X DDR3_A1 52 1700 3500 200 L 40 40 1 1 O
X DDR3_A2 66 1700 3400 200 L 40 40 1 1 O
X DDR3_A3 65 1700 3300 200 L 40 40 1 1 O
X DDR3_A4 51 1700 3200 200 L 40 40 1 1 O
X DDR3_A5 67 1700 3100 200 L 40 40 1 1 O
X DDR3_A6 54 1700 3000 200 L 40 40 1 1 O
X DDR3_A7 71 1700 2900 200 L 40 40 1 1 O
X DDR3_A8 55 1700 2800 200 L 40 40 1 1 O
X DDR3_A9 69 1700 2700 200 L 40 40 1 1 O
X DDR3_A10 48 1700 2600 200 L 40 40 1 1 O
X DDR3_A11 56 1700 2500 200 L 40 40 1 1 O
X DDR3_A12 50 1700 2400 200 L 40 40 1 1 O
X DDR3_A13 68 1700 2300 200 L 40 40 1 1 O
X DDR3_A14 57 1700 2200 200 L 40 40 1 1 O
X DDR3_BA0 63 1700 2000 200 L 40 40 1 1 O
X DDR3_BA1 49 1700 1900 200 L 40 40 1 1 O
X DDR3_BA2 61 1700 1800 200 L 40 40 1 1 O
X DDR3_CAS 59 1700 1300 200 L 40 40 1 1 O
X DDR3_CK 45 1700 1700 200 L 40 40 1 1 O
X DDR3_CKE 47 1700 1500 200 L 40 40 1 1 O
X DDR3_CK_N 46 1700 1600 200 L 40 40 1 1 O
X DDR3_D0 22 1700 5300 200 L 40 40 1 1 B
X DDR3_D1 40 1700 5200 200 L 40 40 1 1 B
X DDR3_D2 21 1700 5100 200 L 40 40 1 1 B
X DDR3_D3 41 1700 5000 200 L 40 40 1 1 B
X DDR3_D4 19 1700 4900 200 L 40 40 1 1 B
X DDR3_D5 44 1700 4800 200 L 40 40 1 1 B
X DDR3_D6 20 1700 4700 200 L 40 40 1 1 B
X DDR3_D7 42 1700 4600 200 L 40 40 1 1 B
X DDR3_D8 37 1700 4500 200 L 40 40 1 1 B
X DDR3_D9 25 1700 4400 200 L 40 40 1 1 B
X DDR3_D10 39 1700 4300 200 L 40 40 1 1 B
X DDR3_D11 24 1700 4200 200 L 40 40 1 1 B
X DDR3_D12 36 1700 4100 200 L 40 40 1 1 B
X DDR3_D13 26 1700 4000 200 L 40 40 1 1 B
X DDR3_D14 38 1700 3900 200 L 40 40 1 1 B
X DDR3_D15 27 1700 3800 200 L 40 40 1 1 B
X DDR3_DM0 29 1700 1000 200 L 40 40 1 1 O
X DDR3_DM1 28 1700 900 200 L 40 40 1 1 O
X DDR3_DQS0 31 1700 800 200 L 40 40 1 1 B
X DDR3_DQS0_N 32 1700 700 200 L 40 40 1 1 B
X DDR3_DQS1 33 1700 600 200 L 40 40 1 1 B
X DDR3_DQS1_N 34 1700 500 200 L 40 40 1 1 B
X DDR3_ODT 72 1700 400 200 L 40 40 1 1 O
X DDR3_RAS 58 1700 1200 200 L 40 40 1 1 O
X DDR3_RST 70 1700 1400 200 L 40 40 1 1 O
X DDR3_WE 60 1700 1100 200 L 40 40 1 1 O
X DZQ 17 1700 100 200 L 40 40 1 1 B
X GND GND_PAD -1700 2100 200 R 40 40 1 1 I
X HPBP 75 -1700 -1100 200 R 40 40 1 1 O
X HPCOM 77 -1700 -900 200 R 40 40 1 1 O
X HPOUTL 74 -1700 -800 200 R 40 40 1 1 O
X HPOUTR 78 -1700 -1000 200 R 40 40 1 1 O
X LRADC 86 -1700 -1500 200 R 40 40 1 1 I
X MICIN1 84 -1700 -400 200 R 40 40 1 1 I
X NC 99 -1700 -2300 200 R 40 40 1 1 U
X NMI_N 158 -1700 1400 200 R 40 40 1 1 I
X PB0/TWI0-SCK 101 -1700 -2600 200 R 40 40 1 1 B
X PB1/TWI0-SDA 102 -1700 -2700 200 R 40 40 1 1 B
X PB2/PWM/SPI2_MOSI/EINT16 103 -1700 -2800 200 R 40 40 1 1 B
X PB3/IR_TX/SPI2_MISO/EINT17 150 -1700 -2900 200 R 40 40 1 1 B
X PB4/IR_RX/EINT18 104 -1700 -3000 200 R 40 40 1 1 B
X PB10/SPI2_CS1/EINT24 10 -1700 -3100 200 R 40 40 1 1 B
X PB15/TWI1_SCK 105 -1700 -3200 200 R 40 40 1 1 B
X PB16/TWI1_SDA 106 -1700 -3300 200 R 40 40 1 1 B
X PB17/TWI2_SCK 161 -1700 -3400 200 R 40 40 1 1 B
X PB18/TWI2_SDA 160 -1700 -3500 200 R 40 40 1 1 B
X PC0/NWE/SPI0_MOSI 8 -1700 -3700 200 R 40 40 1 1 B
X PC1/NALE/SPI0_MISO 7 -1700 -3800 200 R 40 40 1 1 B
X PC2/NCLE/SPI0_CLK 6 -1700 -3900 200 R 40 40 1 1 B
X PC3/NCE1/SPI0_CS0 3 -1700 -4000 200 R 40 40 1 1 B
X PC4/NCE0 2 -1700 -4100 200 R 40 40 1 1 B
X PC5/NRE 1 -1700 -4200 200 R 40 40 1 1 B
X PC6/NRB0/SDC2_CMD 176 -1700 -4300 200 R 40 40 1 1 B
X PC7/NRB1/SDC2_CLK 175 -1700 -4400 200 R 40 40 1 1 B
X PC8/NDQ0/SDC2_D0 174 -1700 -4500 200 R 40 40 1 1 B
X PC9/NDQ1/SDC2_D1 172 -1700 -4600 200 R 40 40 1 1 B
X PC10/NDQ2/SDC2_D2 171 -1700 -4700 200 R 40 40 1 1 B
X PC11/NDQ3/SDC2_D3 170 -1700 -4800 200 R 40 40 1 1 B
X PC12/NDQ4/SDC2_D4 168 -1700 -4900 200 R 40 40 1 1 B
X PC13/NDQ5/SDC2_D5 167 -1700 -5000 200 R 40 40 1 1 B
X PC14/NDQ6/SDC2_D6 166 -1700 -5100 200 R 40 40 1 1 B
X PC15/NDQ7/SDC2_D7 165 -1700 -5200 200 R 40 40 1 1 B
X PC19/NDQS 162 -1700 -5300 200 R 40 40 1 1 B
X PD2/LCD_D2 148 1700 -200 200 L 40 40 1 1 B
X PD3/LCD_D3 147 1700 -300 200 L 40 40 1 1 B
X PD4/LCD_D4 146 1700 -400 200 L 40 40 1 1 B
X PD5/LCD_D5 145 1700 -500 200 L 40 40 1 1 B
X PD6/LCD_D6 144 1700 -600 200 L 40 40 1 1 B
X PD7/LCD_D7 143 1700 -700 200 L 40 40 1 1 B
X PD10/LCD_D10 141 1700 -800 200 L 40 40 1 1 B
X PD11/LCD_D11 140 1700 -900 200 L 40 40 1 1 B
X PD12/LCD_D12 139 1700 -1000 200 L 40 40 1 1 B
X PD13/LCD_D13 138 1700 -1100 200 L 40 40 1 1 B
X PD14/LCD_D14 137 1700 -1200 200 L 40 40 1 1 B
X PD15/LCD_D15 136 1700 -1300 200 L 40 40 1 1 B
X PD18/LCD_D18 135 1700 -1400 200 L 40 40 1 1 B
X PD19/LCD_D19 134 1700 -1500 200 L 40 40 1 1 B
X PD20/LCD_D20 133 1700 -1600 200 L 40 40 1 1 B
X PD21/LCD_D21 132 1700 -1700 200 L 40 40 1 1 B
X PD22/LCD_D22 131 1700 -1800 200 L 40 40 1 1 B
X PD23/LCD_D23 130 1700 -1900 200 L 40 40 1 1 B
X PD24/LCD_CLK 129 1700 -2000 200 L 40 40 1 1 B
X PD25/LCD_DE 128 1700 -2100 200 L 40 40 1 1 B
X PD26/LCD_HSYNC 127 1700 -2200 200 L 40 40 1 1 B
X PD27/LCD_VSYNC 126 1700 -2300 200 L 40 40 1 1 B
X PE0/CSI_PCLK/SPI2_CS0/EINT14 114 1700 -2500 200 L 40 40 1 1 B
X PE1/CSI_MCLK/SPI2_CLK/EINT15 115 1700 -2600 200 L 40 40 1 1 B
X PE2/CSI_HSYNC/SPI2_MOSI 116 1700 -2700 200 L 40 40 1 1 B
X PE3/CSI_VSYNC/SPI2_MISO 117 1700 -2800 200 L 40 40 1 1 B
X PE4/CSI_D0/SDC2_D0 118 1700 -2900 200 L 40 40 1 1 B
X PE5/CSI_D1/SDC2_D1 119 1700 -3000 200 L 40 40 1 1 B
X PE6/CSI_D2/SDC2_D2 120 1700 -3100 200 L 40 40 1 1 B
X PE7/CSI_D3/SDC2_D3 121 1700 -3200 200 L 40 40 1 1 B
X PE8/CSI_D4/SDC2_CMD 122 1700 -3300 200 L 40 40 1 1 B
X PE9/CSI_D5/SDC2_CLK 123 1700 -3400 200 L 40 40 1 1 B
X PE10/CSI_D6/UART1_TX 124 1700 -3500 200 L 40 40 1 1 B
X PE11/CSI_D7/UART1_RX 125 1700 -3600 200 L 40 40 1 1 B
X PF0/SDC0_D1/JTAG_TMS 107 1700 -3800 200 L 40 40 1 1 B
X PF1/SDC0_D0/JTAG_TDI 108 1700 -3900 200 L 40 40 1 1 B
X PF2/SDC0_CLK/UART0_TX 110 1700 -4000 200 L 40 40 1 1 B
X PF3/SDC0_CMD/JTAG_TDO 111 1700 -4100 200 L 40 40 1 1 B
X PF4/SDC0_D3/UART0_RX 112 1700 -4200 200 L 40 40 1 1 B
X PF5/SDC0_D2/JTAG_TCK 113 1700 -4300 200 L 40 40 1 1 B
X PG0/EINT0 155 1700 -4500 200 L 40 40 1 1 B
X PG1/EINT1 154 1700 -4600 200 L 40 40 1 1 B
X PG2/EINT2 153 1700 -4700 200 L 40 40 1 1 B
X PG3/UART1_TX/EINT3 152 1700 -4800 200 L 40 40 1 1 B
X PG4/UART1_RX/EINT4 151 1700 -4900 200 L 40 40 1 1 B
X PG9/SPI1_CS0/UART3_TX/EINT9 12 1700 -5000 200 L 40 40 1 1 B
X PG10/SPI1_CLK/UART3_RX/EINT10 13 1700 -5100 200 L 40 40 1 1 B
X PG11/SPI1_MOSI/UART3_CTS/EINT11 14 1700 -5200 200 L 40 40 1 1 B
X PG12/SPI1_MISO/UART3_RTS/EINT12 15 1700 -5300 200 L 40 40 1 1 B
X RESET_N 159 -1700 1500 200 R 40 40 1 1 I
X SVREF 18 1700 200 200 L 40 40 1 1 B
X TPX1 89 -1700 -1700 200 R 40 40 1 1 B
X TPX2 87 -1700 -1900 200 R 40 40 1 1 B
X TPY1 90 -1700 -1800 200 R 40 40 1 1 B
X TPY2 88 -1700 -2000 200 R 40 40 1 1 B
X UBOOT 157 -1700 1300 200 R 40 40 1 1 I
X UDM0 93 -1700 0 200 R 40 40 1 1 B
X UDM1 95 -1700 200 200 R 40 40 1 1 B
X UDP0 94 -1700 100 200 R 40 40 1 1 B
X UDP1 96 -1700 300 200 R 40 40 1 1 B
X V33_HP 76 -1700 -700 200 R 40 40 1 1 W
X V33_USB 97 -1700 500 200 R 40 40 1 1 B
X VCC1 5 -1700 5300 200 R 40 40 1 1 W
X VCC1_DRAM 23 -1700 3300 200 R 40 40 1 1 W
X VCC2 100 -1700 5200 200 R 40 40 1 1 W
X VCC2_DRAM 30 -1700 3200 200 R 40 40 1 1 W
X VCC3 142 -1700 5100 200 R 40 40 1 1 W
X VCC3_DRAM 43 -1700 3100 200 R 40 40 1 1 W
X VCC4 163 -1700 5000 200 R 40 40 1 1 W
X VCC4_DRAM 53 -1700 3000 200 R 40 40 1 1 W
X VCC5_DRAM 62 -1700 2900 200 R 40 40 1 1 W
X VDD1_CPU 4 -1700 4800 200 R 40 40 1 1 W
X VDD1_INT 35 -1700 3900 200 R 40 40 1 1 W
X VDD2_CPU 9 -1700 4700 200 R 40 40 1 1 W
X VDD2_INT 73 -1700 3800 200 R 40 40 1 1 W
X VDD3-INT 98 -1700 3700 200 R 40 40 1 1 W
X VDD3_CPU 11 -1700 4600 200 R 40 40 1 1 W
X VDD4_CPU 16 -1700 4500 200 R 40 40 1 1 W
X VDD4_INT 109 -1700 3600 200 R 40 40 1 1 W
X VDD5_CPU 156 -1700 4400 200 R 40 40 1 1 W
X VDD5_INT 149 -1700 3500 200 R 40 40 1 1 W
X VDD6_CPU 164 -1700 4300 200 R 40 40 1 1 W
X VDD7_CPU 169 -1700 4200 200 R 40 40 1 1 W
X VDD8_CPU 173 -1700 4100 200 R 40 40 1 1 W
X VMIC 85 -1700 -300 200 R 40 40 1 1 W
X VRA1 83 -1700 900 200 R 40 40 1 1 B
X VRA2 82 -1700 800 200 R 40 40 1 1 B
X VRP 80 -1700 1100 200 R 40 40 1 1 B
X X24MIN 92 -1700 1900 200 R 40 40 1 1 I
X X24MOUT 91 -1700 1700 200 R 40 40 1 1 O
ENDDRAW
ENDDEF
#End Library