cv32e41p_manifest.flist

///////////////////////////////////////////////////////////////////////////////
//
// Copyright 2020 OpenHW Group
//
// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
//     https://solderpad.org/licenses/
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//
///////////////////////////////////////////////////////////////////////////////
//
// Manifest for the CV32E41P RTL model.
//   - Intended to be used by both synthesis and simulation.
//   - Relevent synthesis and simulation scripts/Makefiles must set the shell
//     ENV variable DESIGN_RTL_DIR as required.
//
///////////////////////////////////////////////////////////////////////////////

+incdir+${DESIGN_RTL_DIR}/include
+incdir+${DESIGN_RTL_DIR}/../bhv
+incdir+${DESIGN_RTL_DIR}/../bhv/include
+incdir+${DESIGN_RTL_DIR}/../sva

${DESIGN_RTL_DIR}/include/cv32e41p_apu_core_pkg.sv
${DESIGN_RTL_DIR}/include/cv32e41p_fpu_pkg.sv
${DESIGN_RTL_DIR}/include/cv32e41p_pkg.sv
${DESIGN_RTL_DIR}/../bhv/include/cv32e41p_tracer_pkg.sv
${DESIGN_RTL_DIR}/cv32e41p_if_stage.sv
${DESIGN_RTL_DIR}/cv32e41p_cs_registers.sv
${DESIGN_RTL_DIR}/cv32e41p_register_file_ff.sv
${DESIGN_RTL_DIR}/cv32e41p_load_store_unit.sv
${DESIGN_RTL_DIR}/cv32e41p_id_stage.sv
${DESIGN_RTL_DIR}/cv32e41p_aligner.sv
${DESIGN_RTL_DIR}/cv32e41p_decoder.sv
${DESIGN_RTL_DIR}/cv32e41p_compressed_decoder.sv
${DESIGN_RTL_DIR}/cv32e41p_fifo.sv
${DESIGN_RTL_DIR}/cv32e41p_prefetch_buffer.sv
${DESIGN_RTL_DIR}/cv32e41p_hwloop_regs.sv
${DESIGN_RTL_DIR}/cv32e41p_mult.sv
${DESIGN_RTL_DIR}/cv32e41p_int_controller.sv
${DESIGN_RTL_DIR}/cv32e41p_ex_stage.sv
${DESIGN_RTL_DIR}/cv32e41p_alu_div.sv
${DESIGN_RTL_DIR}/cv32e41p_alu.sv
${DESIGN_RTL_DIR}/cv32e41p_ff_one.sv
${DESIGN_RTL_DIR}/cv32e41p_popcnt.sv
${DESIGN_RTL_DIR}/cv32e41p_apu_disp.sv
${DESIGN_RTL_DIR}/cv32e41p_controller.sv
${DESIGN_RTL_DIR}/cv32e41p_obi_interface.sv
${DESIGN_RTL_DIR}/cv32e41p_prefetch_controller.sv
${DESIGN_RTL_DIR}/cv32e41p_sleep_unit.sv
${DESIGN_RTL_DIR}/cv32e41p_core.sv
${DESIGN_RTL_DIR}/../bhv/cv32e41p_sim_clock_gate.sv
${DESIGN_RTL_DIR}/../bhv/cv32e41p_wrapper.sv