CV32E40S is a small and efficient, 32-bit, in-order RISC-V core with a 4-stage pipeline that implements the RV32IMCXsecureZce_Zicsr_Zifencei instruction set architecture. The CV32E40S core is aimed at security applications and offers both Machine mode and User mode, an enhanced PMP, as well as various anti-tampering features.
It started its life as a fork of the OpenHW CV32E40P core that in its turn was based on the RI5CY core from the PULP platform team.
The CV32E40S user manual can be found in the docs folder and it is captured in reStructuredText, rendered to html using Sphinx. These documents are viewable using readthedocs and can be viewed here.
The verification environment for the CV32E40S is not in this Repository.
The verification environment for this core as well as other cores in the OpenHW Group CORE-V family is at the core-v-verif repository on GitHub.
The Makefiles supported in the core-v-verif project automatically clone the appropriate version of the cv32e40s RTL sources.
Example synthesis constraints for the CV32E40S are provided.
We highly appreciate community contributions. We are currently using the lowRISC contribution guide.
To ease our work of reviewing your contributions, please:
- Create your own fork to commit your changes and then open a Pull Request.
- Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit!
- Write meaningful commit messages. For more information, please check out the the Ibex contribution guide.
- If asked to modify your changes, do fixup your commits and rebase your branch to maintain a clean history.
When contributing SystemVerilog source code, please try to be consistent and adhere to the lowRISC Verilog coding style guide.
To get started, please check out the "Good First Issue" list.
If you find any problems or issues with CV32E40S or the documentation, please check out the issue tracker and create a new issue if your problem is not yet tracked.