New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Clock Reset Power schema #18

Open

drom opened this issue Apr 2, 2020 · 3 comments

Member

drom commented Apr 2, 2020

Create a schema to capture Clock, Reset, Power intent.

mwachs5 commented Apr 2, 2020

hopefully this can align nicely with UPF. Can we refer to UPF specification to see what concepts we should be capturing?

Member Author

drom commented Apr 2, 2020

Yes, it is. We have UPF-DUH import tool here https://github.com/sifive/upf

mwachs5 commented Apr 16, 2020

we need to know RE clocks and resets:

reset polarity
reset synchronous-to-what-clock
reset type (are the flops connected to this flop sync. async, both, other...)

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment