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RISC-V linker issues for 32-bit simulation #76

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nomadeel opened this issue May 24, 2021 · 1 comment
Open

RISC-V linker issues for 32-bit simulation #76

nomadeel opened this issue May 24, 2021 · 1 comment

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@nomadeel
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As a result from #75, we discovered that having a contiguous blob of code + ro-data presents some problems for 32-bit RISC-V simulation on QEMU. The simulation in question manages to start up the elfloader only for it to freeze up near the beginning when it's printing information about the HART that it is running on.

@kent-mcleod
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It's highly likely that this issue is caused by the bss section not being initialized to 0 causing some issue with setup.

  • The spike platforms aren't configured to set CONFIG_IMAGE_BINARY so clear_bss wouldn't be called.
  • The opensbi compilation converts the elfloader elf into a binary image which would remove the .bss section from the end of the file as it's allocated but has default contents
  • When the image is initialized by the loader, the memory isn't zeroed and may have different values.
  • Rearranging the linker script to put the .rodata sections after the bss cause the bss sections to become contents within the binary file and would then be initialized by the loading.

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