diff --git a/.github/workflows/lava-ci.yml b/.github/workflows/lava-ci.yml
index c0bd333..e4ab545 100644
--- a/.github/workflows/lava-ci.yml
+++ b/.github/workflows/lava-ci.yml
@@ -41,7 +41,6 @@ jobs:
           ghcup set ghc ${{ matrix.compilerVersion }}
           ghc --version
           ghcup install cabal 3.10.3.0
-          ls -a ~
           cabal v2-update
           sudo apt-get update
           sudo apt-get install -y verilator
@@ -59,4 +58,4 @@ jobs:
         run: |
           cd source
           cabal v2-test
-          verilator +1800-2017ext+sv verilator.vlt --binary --trace -Wall --top-module nandgate_sim nandgate.sv nandgate_sim.sv
+
diff --git a/test-verilator/Main.hs b/test-verilator/Main.hs
index b3fd3f5..70bb954 100644
--- a/test-verilator/Main.hs
+++ b/test-verilator/Main.hs
@@ -1,9 +1,15 @@
 module Main (main) where
 
 import Lava
+import System.Process
+-- import Data.VCD
 import Lava.Examples.NandGate
 
 main :: IO ()
 main
   = do writeSystemVerilog nandGateTop
        writeSystemVerilogSimulation nandGateTop [[L, L], [H, L], [L, H], [H, H]]
+       callProcess "verilator" ["+1800-2017ext+sv", "verilator.vlt", "--binary",  "--trace",  "-Wall", "--top-module",  "nandgate_sim",  "nandgate.sv", "nandgate_sim.sv"]
+       callProcess "obj_dir/Vnandgate_sim" ["+trace"]
+       -- vcd_contents <- readFile "nandgate_sim.vcd"
+       -- putStrLn (show (parseVCD vcd_contents))
\ No newline at end of file
diff --git a/xilinx-lava.cabal b/xilinx-lava.cabal
index 297c35d..4d07573 100644
--- a/xilinx-lava.cabal
+++ b/xilinx-lava.cabal
@@ -146,4 +146,6 @@ test-suite test-verilator
     build-depends:
         base >= 4.17.2 && <= 4.20.0.0,
         bitvec >= 1.1.2.0,
-        xilinx-lava
+        xilinx-lava,
+        process,
+        vcd ^>=0.2.2,