From 9165d10a7ba0be322e76a285008c86e323167239 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Eduardo=20S=C3=A1nchez=20Mu=C3=B1oz?= Date: Tue, 3 Oct 2023 18:14:01 +0200 Subject: [PATCH 1/2] =?UTF-8?q?Fix=20typos=20`*ucom`=20=E2=86=92=20`ucom*`?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- src/shims/x86/sse.rs | 2 +- src/shims/x86/sse2.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/shims/x86/sse.rs b/src/shims/x86/sse.rs index de1e695b6d..0e51a73d09 100644 --- a/src/shims/x86/sse.rs +++ b/src/shims/x86/sse.rs @@ -141,7 +141,7 @@ pub(super) trait EvalContextExt<'mir, 'tcx: 'mir>: let left = this.read_scalar(&this.project_index(&left, 0)?)?.to_f32()?; let right = this.read_scalar(&this.project_index(&right, 0)?)?.to_f32()?; - // The difference between the com* and *ucom variants is signaling + // The difference between the com* and ucom* variants is signaling // of exceptions when either argument is a quiet NaN. We do not // support accessing the SSE status register from miri (or from Rust, // for that matter), so we treat equally both variants. diff --git a/src/shims/x86/sse2.rs b/src/shims/x86/sse2.rs index 2ef6a9b59e..a27d37d0ff 100644 --- a/src/shims/x86/sse2.rs +++ b/src/shims/x86/sse2.rs @@ -637,7 +637,7 @@ pub(super) trait EvalContextExt<'mir, 'tcx: 'mir>: let left = this.read_scalar(&this.project_index(&left, 0)?)?.to_f64()?; let right = this.read_scalar(&this.project_index(&right, 0)?)?.to_f64()?; - // The difference between the com* and *ucom variants is signaling + // The difference between the com* and ucom* variants is signaling // of exceptions when either argument is a quiet NaN. We do not // support accessing the SSE status register from miri (or from Rust, // for that matter), so we treat equally both variants. From 42f0df5aafc95960818542f2dbdc34b2a9689ea0 Mon Sep 17 00:00:00 2001 From: Ralf Jung Date: Tue, 3 Oct 2023 20:00:48 +0200 Subject: [PATCH 2/2] wording tweaks --- src/shims/x86/sse.rs | 2 +- src/shims/x86/sse2.rs | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/shims/x86/sse.rs b/src/shims/x86/sse.rs index 0e51a73d09..fa722f4b75 100644 --- a/src/shims/x86/sse.rs +++ b/src/shims/x86/sse.rs @@ -144,7 +144,7 @@ pub(super) trait EvalContextExt<'mir, 'tcx: 'mir>: // The difference between the com* and ucom* variants is signaling // of exceptions when either argument is a quiet NaN. We do not // support accessing the SSE status register from miri (or from Rust, - // for that matter), so we treat equally both variants. + // for that matter), so we treat both variants equally. let res = match unprefixed_name { "comieq.ss" | "ucomieq.ss" => left == right, "comilt.ss" | "ucomilt.ss" => left < right, diff --git a/src/shims/x86/sse2.rs b/src/shims/x86/sse2.rs index a27d37d0ff..261c947c8e 100644 --- a/src/shims/x86/sse2.rs +++ b/src/shims/x86/sse2.rs @@ -640,7 +640,7 @@ pub(super) trait EvalContextExt<'mir, 'tcx: 'mir>: // The difference between the com* and ucom* variants is signaling // of exceptions when either argument is a quiet NaN. We do not // support accessing the SSE status register from miri (or from Rust, - // for that matter), so we treat equally both variants. + // for that matter), so we treat both variants equally. let res = match unprefixed_name { "comieq.sd" | "ucomieq.sd" => left == right, "comilt.sd" | "ucomilt.sd" => left < right,