From ffe20a55b523d7210b74f9d29d18dc38844411b7 Mon Sep 17 00:00:00 2001
From: rmsyn <github@weathered-steel.dev>
Date: Fri, 8 Nov 2024 02:56:27 +0000
Subject: [PATCH 1/2] riscv: define mip using CSR macros

Uses CSR helper macros to define the `mip` register.
---
 riscv/src/register/mip.rs | 63 +++++++++++++++++----------------------
 1 file changed, 27 insertions(+), 36 deletions(-)

diff --git a/riscv/src/register/mip.rs b/riscv/src/register/mip.rs
index b5d22580..dcf126e7 100644
--- a/riscv/src/register/mip.rs
+++ b/riscv/src/register/mip.rs
@@ -1,56 +1,47 @@
 //! mip register
 
-/// mip register
-#[derive(Clone, Copy, Debug)]
-pub struct Mip {
-    bits: usize,
+read_write_csr! {
+    /// `mip` register
+    Mip: 0x344,
+    mask: 0xaaa,
 }
 
-impl Mip {
-    /// Returns the contents of the register as raw bits
-    #[inline]
-    pub fn bits(&self) -> usize {
-        self.bits
-    }
-
+read_write_csr_field! {
+    Mip,
     /// Supervisor Software Interrupt Pending
-    #[inline]
-    pub fn ssoft(&self) -> bool {
-        self.bits & (1 << 1) != 0
-    }
+    ssoft: 1,
+}
 
+read_only_csr_field! {
+    Mip,
     /// Machine Software Interrupt Pending
-    #[inline]
-    pub fn msoft(&self) -> bool {
-        self.bits & (1 << 3) != 0
-    }
+    msoft: 3,
+}
 
+read_write_csr_field! {
+    Mip,
     /// Supervisor Timer Interrupt Pending
-    #[inline]
-    pub fn stimer(&self) -> bool {
-        self.bits & (1 << 5) != 0
-    }
+    stimer: 5,
+}
 
+read_only_csr_field! {
+    Mip,
     /// Machine Timer Interrupt Pending
-    #[inline]
-    pub fn mtimer(&self) -> bool {
-        self.bits & (1 << 7) != 0
-    }
+    mtimer: 7,
+}
 
+read_write_csr_field! {
+    Mip,
     /// Supervisor External Interrupt Pending
-    #[inline]
-    pub fn sext(&self) -> bool {
-        self.bits & (1 << 9) != 0
-    }
+    sext: 9,
+}
 
+read_only_csr_field! {
+    Mip,
     /// Machine External Interrupt Pending
-    #[inline]
-    pub fn mext(&self) -> bool {
-        self.bits & (1 << 11) != 0
-    }
+    mext: 11,
 }
 
-read_csr_as!(Mip, 0x344);
 set!(0x344);
 clear!(0x344);
 

From 803a68c115d0ed177c8f272738ca2a3c20994691 Mon Sep 17 00:00:00 2001
From: rmsyn <github@weathered-steel.dev>
Date: Fri, 8 Nov 2024 02:58:18 +0000
Subject: [PATCH 2/2] riscv: add mip unit tests

Adds basic unit tests for the `mip` register.
---
 riscv/CHANGELOG.md        |  1 +
 riscv/src/register/mip.rs | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)

diff --git a/riscv/CHANGELOG.md b/riscv/CHANGELOG.md
index d0eb9ab1..67fbb920 100644
--- a/riscv/CHANGELOG.md
+++ b/riscv/CHANGELOG.md
@@ -22,6 +22,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Use CSR helper macros to define `mie` register
 - Use CSR helper macros to define `mimpid` register
 - Use CSR helper macros to define `misa` register
+- Use CSR helper macros to define `mip` register
 
 ## [v0.12.1] - 2024-10-20
 
diff --git a/riscv/src/register/mip.rs b/riscv/src/register/mip.rs
index dcf126e7..bfcb8936 100644
--- a/riscv/src/register/mip.rs
+++ b/riscv/src/register/mip.rs
@@ -54,3 +54,25 @@ set_clear_csr!(
 set_clear_csr!(
     /// Supervisor External Interrupt Pending
     , set_sext, clear_sext, 1 << 9);
+
+#[cfg(test)]
+mod tests {
+    use super::*;
+
+    #[test]
+    fn test_mip() {
+        let mut m = Mip::from_bits(0);
+
+        test_csr_field!(m, ssoft);
+        test_csr_field!(m, stimer);
+        test_csr_field!(m, sext);
+
+        assert!(!m.msoft());
+        assert!(!m.mtimer());
+        assert!(!m.mext());
+
+        assert!(Mip::from_bits(1 << 3).msoft());
+        assert!(Mip::from_bits(1 << 7).mtimer());
+        assert!(Mip::from_bits(1 << 11).mext());
+    }
+}