From f90bc5f7ada43e759b983c658e55fe29c8bb1f92 Mon Sep 17 00:00:00 2001 From: Phil Tokumaru Date: Sun, 30 Jun 2024 15:31:08 -0700 Subject: [PATCH] Add DSHOT support and associated changes --- common/Varmint.cpp | 134 ++-------- common/drivers/Driver.h | 3 +- common/drivers/Pwm.cpp | 117 +++++---- common/drivers/Pwm.h | 252 +++++++++++------- common/drivers/Time64.h | 1 - common/drivers/misc.cpp | 15 +- pixracer_pro/.settings/language.settings.xml | 4 +- pixracer_pro/Core/Inc/stm32h7xx_it.h | 2 +- pixracer_pro/Core/Src/main.c | 16 +- pixracer_pro/Core/Src/stm32h7xx_hal_msp.c | 215 +++++++-------- pixracer_pro/Core/Src/stm32h7xx_it.c | 28 +- pixracer_pro/pixracer_pro.ioc | 182 ++++++------- pixracer_pro/specific/BoardConfig.h | 53 ++-- pixracer_pro/specific/Varmint.h | 2 + test/board.h | 10 +- varmint_10X/.settings/language.settings.xml | 4 +- varmint_10X/Core/Inc/stm32h7xx_hal_conf.h | 2 +- varmint_10X/Core/Src/main.c | 8 +- varmint_10X/Core/Src/stm32h7xx_hal_msp.c | 103 ++++---- varmint_10X/Core/Src/stm32h7xx_it.c | 8 +- varmint_10X/specific/BoardConfig.h | 59 ++--- varmint_10X/specific/Varmint.h | 2 + varmint_10X/varmint_10X.ioc | 263 ++++++++++--------- 23 files changed, 749 insertions(+), 734 deletions(-) diff --git a/common/Varmint.cpp b/common/Varmint.cpp index e0a0637..c15917f 100644 --- a/common/Varmint.cpp +++ b/common/Varmint.cpp @@ -390,22 +390,35 @@ float Varmint::rc_read(uint8_t chan) ever_read = true; } - if ((chan < PWM_CHANNELS) & ever_read) + if ((chan < RC_PACKET_CHANNELS) & ever_read) return p.chan[chan]; return -1; // out of range or no data in p } /////////////////////////////////////////////////////////////////////////////////////////////// // PWM + +// legacy, all channels are pwm and set to the same 'refresh_rate' void Varmint::pwm_init(uint32_t refresh_rate, uint16_t idle_pwm) { for (int ch = 0; ch < PWM_CHANNELS; ch++) pwm_.disable(ch); for (int ch = 0; ch < PWM_CHANNELS; ch++) - pwm_.set_rate(ch, refresh_rate); + { + pwm_.setRate(ch, refresh_rate); + if(idle_pwm==0) pwm_.writeUs(ch, 0); // OFF + else pwm_.write(ch, 0.0); // Channel minimum value + } for (int ch = 0; ch < PWM_CHANNELS; ch++) pwm_.enable(ch); } + +void Varmint::pwm_init(const float *rate, uint32_t channels) +{ + pwm_.updateConfig(rate,channels); +} + + void Varmint::pwm_disable(void) { for (int ch = 0; ch < PWM_CHANNELS; ch++) @@ -416,6 +429,13 @@ void Varmint::pwm_write(uint8_t ch, float value) pwm_.write(ch, value); } +void Varmint::pwm_write(float *value, uint32_t channels) +{ + pwm_.write(value, channels); +} + + + /////////////////////////////////////////////////////////////////////////////////////////////// // LEDs void Varmint::led0_on() // Red LED @@ -491,113 +511,3 @@ bool Varmint::memory_write(const void *src, size_t len) /////////////////////////////////////////////////////////////////////////////////////////////// // Helper functions (not part of parent class) - -//uint32_t Varmint::pwm_init_timers(uint32_t servo_pwm_period_us) -//{ -// { -// TIM_MasterConfigTypeDef sMasterConfig = {0}; -// TIM_OC_InitTypeDef sConfigOC = {0}; -// TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; -// -// htim1.Instance = TIM1; -// htim1.Init.Prescaler = (SERVO_PWM_CLK_DIV); -// htim1.Init.CounterMode = TIM_COUNTERMODE_UP; -// htim1.Init.Period = servo_pwm_period_us; -// htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; -// htim1.Init.RepetitionCounter = 0; -// htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; -// if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) -// return DRIVER_HAL_ERROR; -// sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; -// sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; -// sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; -// if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) -// return DRIVER_HAL_ERROR; -// sConfigOC.OCMode = TIM_OCMODE_PWM1; -// sConfigOC.Pulse = (SERVO_PWM_CENTER); -// sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; -// sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; -// sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; -// sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; -// sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; -// if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) -// return DRIVER_HAL_ERROR; -// if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) -// return DRIVER_HAL_ERROR; -// if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) -// return DRIVER_HAL_ERROR; -// if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) -// return DRIVER_HAL_ERROR; -// sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; -// sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; -// sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; -// sBreakDeadTimeConfig.DeadTime = 0; -// sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; -// sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; -// sBreakDeadTimeConfig.BreakFilter = 0; -// sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; -// sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; -// sBreakDeadTimeConfig.Break2Filter = 0; -// sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; -// if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) -// return DRIVER_HAL_ERROR; -// HAL_TIM_MspPostInit(&htim1); -// } -//#if defined(htim3) -// { -// TIM_MasterConfigTypeDef sMasterConfig = {0}; -// TIM_OC_InitTypeDef sConfigOC = {0}; -// htim3.Instance = TIM3; -// htim3.Init.Prescaler = (SERVO_PWM_CLK_DIV); -// htim3.Init.CounterMode = TIM_COUNTERMODE_UP; -// htim3.Init.Period = servo_pwm_period_us; -// htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; -// htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; -// if (HAL_TIM_PWM_Init(&htim3) != HAL_OK) -// return DRIVER_HAL_ERROR; -// sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; -// sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; -// if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) -// return DRIVER_HAL_ERROR; -// sConfigOC.OCMode = TIM_OCMODE_PWM1; -// sConfigOC.Pulse = (SERVO_PWM_CENTER); -// sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; -// sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; -// if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) -// return DRIVER_HAL_ERROR; -// if (HAL_TIM_PWM_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) -// return DRIVER_HAL_ERROR; -// HAL_TIM_MspPostInit(&htim3); -// } -//#endif -// { -// TIM_MasterConfigTypeDef sMasterConfig = {0}; -// TIM_OC_InitTypeDef sConfigOC = {0}; -// htim4.Instance = TIM4; -// htim4.Init.Prescaler = (SERVO_PWM_CLK_DIV); -// htim4.Init.CounterMode = TIM_COUNTERMODE_UP; -// htim4.Init.Period = servo_pwm_period_us; -// htim4.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; -// htim4.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; -// if (HAL_TIM_PWM_Init(&htim4) != HAL_OK) -// return DRIVER_HAL_ERROR; -// sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; -// sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; -// if (HAL_TIMEx_MasterConfigSynchronization(&htim4, &sMasterConfig) != HAL_OK) -// return DRIVER_HAL_ERROR; -// sConfigOC.OCMode = TIM_OCMODE_PWM1; -// sConfigOC.Pulse = (SERVO_PWM_CENTER); -// sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; -// sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; -// if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) -// return DRIVER_HAL_ERROR; -// if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) -// return DRIVER_HAL_ERROR; -// if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) -// return DRIVER_HAL_ERROR; -// if (HAL_TIM_PWM_ConfigChannel(&htim4, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) -// return DRIVER_HAL_ERROR; -// HAL_TIM_MspPostInit(&htim4); -// } -// return DRIVER_OK; -//} diff --git a/common/drivers/Driver.h b/common/drivers/Driver.h index 1e7b25c..5d56203 100644 --- a/common/drivers/Driver.h +++ b/common/drivers/Driver.h @@ -47,8 +47,7 @@ class Driver { public: - // virtual bool startDma (void)=0; // Called in response to a data ready signal - // virtual void endDma (void)=0; // Called when DMA read is complete + virtual bool display(void) = 0; uint16_t rxFifoCount(void) diff --git a/common/drivers/Pwm.cpp b/common/drivers/Pwm.cpp index bee5ac5..d45481d 100644 --- a/common/drivers/Pwm.cpp +++ b/common/drivers/Pwm.cpp @@ -46,57 +46,82 @@ // 600 600kbit/s 1.25 0.625 1.67 26.72 // 1200 1200kbit/s 0.625 0.313 0.83 13.28 -typedef enum -{ - PWM_STD, - PWM_DSHOT, -} PwmProtocol; - -//typedef struct __attribute__((__packed__)) -//{ -// TIM_HandleTypeDef *htim; -// uint16_t channel; -// uint16_t min; -// uint16_t center; -// uint16_t max; -//} PwmChannelCfg; - -typedef struct __attribute__((__packed__)) +__attribute__((section(".data"))) PwmBlockStructure pwm_init[PWM_TIMER_BLOCKS] = PWM_INIT_DEFINE; + +__attribute__((section("my_dma_buffers"))) +__attribute__((aligned(32))) static uint32_t pwm_dma_buf[PWM_TIMER_BLOCKS][PWM_DMA_BUFFER_LEN] = {0}; + + +void Pwm::updateConfig(const float *rate, uint32_t channels) { - TIM_TypeDef *instance; - PwmProtocol protocol; - uint32_t period_counts; -} PwmBlockCfg; + channels = (channelsInstance = pwm_blk[bk].instance; - htim->Init.Prescaler = prescaler; + TIM_HandleTypeDef *htim = block_[bk].htim; + + if(htim == &htim1) htim->Instance = TIM1; + else if(htim == &htim3) htim->Instance = TIM3; + else if(htim == &htim4) htim->Instance = TIM4; + else if(htim == &htim8) htim->Instance = TIM8; + else return DRIVER_HAL_ERROR; + + if((block_[bk].rate >= 150000) && (block_[bk].type == PWM_DSHOT)) // DSHOT + { + htim->Init.Prescaler = 0; + htim->Init.Period = (uint64_t)200000000/block_[bk].rate; + } + else if((block_[bk].type == PWM_STANDARD) && (block_[bk].rate < 490)) + { + htim->Init.Prescaler = 199; + htim->Init.Period = (uint64_t)1000000/block_[bk].rate; + } + else + return DRIVER_HAL_ERROR; + htim->Init.CounterMode = TIM_COUNTERMODE_UP; - htim->Init.Period = pwm_blk[bk].period_counts; htim->Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; htim->Init.RepetitionCounter = 0; htim->Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_ENABLE; @@ -108,24 +133,24 @@ uint32_t Pwm::init(void) if (HAL_TIMEx_MasterConfigSynchronization(htim, &sMasterConfig) != HAL_OK) return DRIVER_HAL_ERROR; sConfigOC.OCMode = TIM_OCMODE_PWM1; - // sConfigOC.Pulse = (SERVO_PWM_CENTER); +// sConfigOC.Pulse = 1500; sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; - for(uint8_t ch=0;ch +#define PWM_DMA_BUFFER_LEN 96 + +#define PWM_CHAN_IGNORE (0xFFFFFFFF) + +#define PWM_SERVO_MIN (1000) +#define PWM_SERVO_MAX (2000) + +#define DSHOT_ESC_MIN (48) +#define DSHOT_ESC_MAX (2047) +#define DSHOT_HI (200000000/PWM_DSHOT_RATE_HZ*3/4) +#define DSHOT_LO (200000000/PWM_DSHOT_RATE_HZ*3/8) + +#define PWM_DSHOT_RATE_HZ (300000.0) // baud rate +#define PWM_MKS_RATE_HZ (333.0) +#define PWM_STD_RATE_HZ (50.0) + +typedef enum +{ + PWM_STANDARD, + PWM_DSHOT +} pwm_type; + typedef struct __attribute__((__packed__)) { TIM_HandleTypeDef *htim; - uint16_t channel; - uint16_t min; - uint16_t center; - uint16_t max; -} PwmChannelCfg; + pwm_type type; + float rate; + uint32_t chan[4]; +} PwmBlockStructure; class Pwm { public: uint32_t init(void); + void updateConfig(const float *rate, uint32_t channels); - void enable(uint8_t chan) + void enable(uint32_t chan) { - if(chan_[chan].htim) - HAL_TIM_PWM_Start(chan_[chan].htim, chan_[chan].channel); + if(chan chan_[chan].max) ? chan_[chan].max : us; - __HAL_TIM_SET_COMPARE(chan_[chan].htim, chan_[chan].channel, us); + TIM_HandleTypeDef *htim = htim_[chan]; + if (htim!=nullptr) + { + us = (us < PWM_SERVO_MIN) ? PWM_SERVO_MIN : us; + us = (us > PWM_SERVO_MAX) ? PWM_SERVO_MAX : us; + __HAL_TIM_SET_COMPARE(htim, chan_[chan], us); + } } } - void write(uint8_t chan, double val) + void write(uint32_t chan, float val) { - if (chan_[chan].htim) + if(chan 1) ? 1 : val; - uint16_t us = val * (double)(chan_[chan].max - chan_[chan].min) + chan_[chan].min; + uint32_t us = val * (float)(PWM_SERVO_MAX - PWM_SERVO_MIN) +PWM_SERVO_MIN; writeUs(chan,us); - //__HAL_TIM_SET_COMPARE(chan_[chan].htim, chan_[chan].channel, us); } } + + void write(float *output, uint32_t channels) + { + channels = (channels 1) ? 1 : val; + uint32_t us = val * (float)(PWM_SERVO_MAX- PWM_SERVO_MIN) + PWM_SERVO_MIN; + __HAL_TIM_SET_COMPARE(htim, ch<<2, us); + } + else + { + __HAL_TIM_SET_COMPARE(htim, ch<<2, 0); + } + } + } + else // DSHOT + { + #define NWORDS ((16+1)*4) // 4 channels 16 data bits + 1 end of message bit + HAL_TIM_DMABurst_WriteStop(htim, TIM_DMA_UPDATE); + + // memset(dmaBuf_[bk],0, NWORDS*sizeof(uint32_t)); + for (uint32_t ch=0;ch<4;ch++) + { + uint32_t output_index = block_[bk].chan[ch]; + if(output_index 1) ? 1 : val; + uint32_t value = val * (float)(DSHOT_ESC_MAX - DSHOT_ESC_MIN) + DSHOT_ESC_MIN; + value = (uint32_t)(value)<<1; + uint32_t crc = (value ^ (value >> 4) ^ (value >> 8)) & 0x000F; + value = (value<<4) | crc; + uint32_t mask = 0x00008000; + uint32_t *buf = dmaBuf_[bk]+ch; + + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&(mask>>=1))?DSHOT_HI:DSHOT_LO; + *(buf+=4) = (value&mask)?DSHOT_HI:DSHOT_LO; + *buf =0; + + } + } + HAL_TIM_DMABurst_MultiWriteStart( + htim, TIM_DMABASE_CCR1, TIM_DMA_UPDATE, + (uint32_t *)(dmaBuf_[bk]), TIM_DMABURSTLENGTH_4TRANSFERS, NWORDS); + } + } + + } + // Note this sets the rate for all members of the block. - void set_rate(uint8_t chan, uint32_t rate) + void setRate(uint32_t chan, float rate) + { + if(chan 0) && (rate <= 400)) - chan_[chan].htim->Instance->ARR = 1000000 / rate; + PwmBlockStructure &block = block_[block_index]; + + if ((rate >= 0.0) && (rate <= 490.0)) + { + block.type = PWM_STANDARD; + block.rate = rate; + block.htim->Instance->PSC = 199; + block.htim->Instance->ARR = (uint32_t)(1000000.0/rate+0.99); // assumes dividers are set for 1MHz clock input + } + else if((rate>=150000.0) && (rate<=1200000.0)) + { + block.type = PWM_DSHOT; + block.rate = rate; + block.htim->Instance->PSC = 0; + block.htim->Instance->ARR = (uint32_t)(200000000.0/rate+0.99); // assumes dividers are set for 200MHz clock input + } + } + } } -private: - PwmChannelCfg *chan_; -}; +private: + PwmBlockStructure *block_; + TIM_HandleTypeDef *htim_[PWM_CHANNELS]; + uint32_t chan_[PWM_CHANNELS]; + uint32_t (*dmaBuf_)[PWM_DMA_BUFFER_LEN]; + uint32_t blockIndex_[PWM_CHANNELS]; -// -// -//class Pwm -//{ -// public: -// uint32_t init(TIM_HandleTypeDef *htim, uint16_t chan, uint16_t min, uint16_t center, uint16_t max) -// { -// htim_ = htim; -// chan_ = chan; -// min_ = min; -// center_ = center; -// max_ = max; -// -// disable(); -// writeUs(center_); -// return DRIVER_OK; -// } -// void enable() -// { -// if (htim_) -// { -// HAL_TIM_PWM_Start(htim_, chan_); -// } -// } -// -// void disable() -// { -// if (htim_) -// HAL_TIM_PWM_Stop(htim_, chan_); -// } -// -// void writeUs(uint16_t us) -// { -// if (htim_) -// { -// us = (us < min_) ? min_ : us; -// us = (us > max_) ? max_ : us; -// __HAL_TIM_SET_COMPARE(htim_, chan_, us); -// } -// } -// void write(double val) -// { -// if (htim_) -// { -// val = (val < 0) ? 0 : val; -// val = (val > 1) ? 1 : val; -// uint16_t us = val * (double)(max_ - min_) + min_; -// __HAL_TIM_SET_COMPARE(htim_, chan_, us); -// } -// } -// -// void set_rate(uint32_t rate) -// { -// if ((rate > 0) && (rate <= 400)) -// htim_->Instance->ARR = 1000000 / rate; -// } -// -// private: -// TIM_HandleTypeDef *htim_; -// uint32_t chan_; -// uint16_t min_; // us -// uint16_t center_; // us -// uint16_t max_; // us -//}; +}; #endif /* PWM_H_ */ diff --git a/common/drivers/Time64.h b/common/drivers/Time64.h index 2197ffd..e75af30 100644 --- a/common/drivers/Time64.h +++ b/common/drivers/Time64.h @@ -45,7 +45,6 @@ class Time64 { public: - Time64(){}; uint32_t init(TIM_HandleTypeDef *htim_low, TIM_TypeDef *instance_low, TIM_HandleTypeDef *htim_high, TIM_TypeDef *instance_high) { diff --git a/common/drivers/misc.cpp b/common/drivers/misc.cpp index a21855c..c1adf79 100644 --- a/common/drivers/misc.cpp +++ b/common/drivers/misc.cpp @@ -1,6 +1,6 @@ /** ****************************************************************************** - * File : verbose.c + * File : misc.c * Date : Sep 23, 2023 ****************************************************************************** * @@ -43,15 +43,10 @@ #include -#include - #include -extern Time64 time64; - extern bool verbose; -// extern UART_HandleTypeDef huart1; extern "C" { @@ -129,9 +124,9 @@ void misc_exit_status(uint32_t status) { misc_printf("Exit Status: "); if (status == DRIVER_OK) - misc_printf(" DRIVER_OK"); + misc_printf(" \033[0;42mDRIVER_OK"); else - misc_printf(" DRIVER_ERROR"); + misc_printf(" \033[0;41mDRIVER_ERROR"); if (status & DRIVER_ID_MISMATCH) misc_printf(" DRIVER_ID_MISMATCH"); @@ -155,5 +150,7 @@ void misc_exit_status(uint32_t status) misc_printf(" UBX_FAIL_BAUD_CHANGE"); if (status & VOLTAGE_SET_FAIL) misc_printf(" VOLTAGE_SET_FAIL"); - misc_printf("\n"); + misc_printf("\033[0m\n"); + + if (status != DRIVER_OK && verbose) while(1); //PTT debug only. Removing this line. } diff --git a/pixracer_pro/.settings/language.settings.xml b/pixracer_pro/.settings/language.settings.xml index 8dca5a4..9d5d4f5 100644 --- a/pixracer_pro/.settings/language.settings.xml +++ b/pixracer_pro/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/pixracer_pro/Core/Inc/stm32h7xx_it.h b/pixracer_pro/Core/Inc/stm32h7xx_it.h index 938b74b..81ceef7 100644 --- a/pixracer_pro/Core/Inc/stm32h7xx_it.h +++ b/pixracer_pro/Core/Inc/stm32h7xx_it.h @@ -83,7 +83,7 @@ void DMA2_Stream2_IRQHandler(void); void DMA2_Stream3_IRQHandler(void); void DMA2_Stream4_IRQHandler(void); void DMA2_Stream5_IRQHandler(void); -void DMA2_Stream7_IRQHandler(void); +void DMA2_Stream6_IRQHandler(void); void USART6_IRQHandler(void); void UART7_IRQHandler(void); void UART8_IRQHandler(void); diff --git a/pixracer_pro/Core/Src/main.c b/pixracer_pro/Core/Src/main.c index 0522ead..d76db8f 100644 --- a/pixracer_pro/Core/Src/main.c +++ b/pixracer_pro/Core/Src/main.c @@ -81,6 +81,9 @@ TIM_HandleTypeDef htim5; TIM_HandleTypeDef htim7; TIM_HandleTypeDef htim8; TIM_HandleTypeDef htim12; +DMA_HandleTypeDef hdma_tim1_up; +DMA_HandleTypeDef hdma_tim4_up; +DMA_HandleTypeDef hdma_tim8_up; UART_HandleTypeDef huart4; UART_HandleTypeDef huart7; @@ -90,10 +93,7 @@ UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; UART_HandleTypeDef huart6; DMA_HandleTypeDef hdma_uart4_rx; -DMA_HandleTypeDef hdma_uart7_rx; -DMA_HandleTypeDef hdma_uart8_rx; -DMA_HandleTypeDef hdma_usart1_rx; -DMA_HandleTypeDef hdma_usart3_rx; +DMA_HandleTypeDef hdma_usart2_tx; DMA_HandleTypeDef hdma_usart6_rx; PCD_HandleTypeDef hpcd_USB_OTG_FS; @@ -1841,14 +1841,14 @@ void MX_DMA_Init(void) HAL_NVIC_SetPriority(DMA2_Stream3_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA2_Stream3_IRQn); /* DMA2_Stream4_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA2_Stream4_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA2_Stream4_IRQn); /* DMA2_Stream5_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); - /* DMA2_Stream7_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 5, 0); - HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); + /* DMA2_Stream6_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); + HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); } diff --git a/pixracer_pro/Core/Src/stm32h7xx_hal_msp.c b/pixracer_pro/Core/Src/stm32h7xx_hal_msp.c index 8b0e7c5..bff581d 100644 --- a/pixracer_pro/Core/Src/stm32h7xx_hal_msp.c +++ b/pixracer_pro/Core/Src/stm32h7xx_hal_msp.c @@ -48,15 +48,15 @@ extern DMA_HandleTypeDef hdma_spi6_rx; extern DMA_HandleTypeDef hdma_spi6_tx; -extern DMA_HandleTypeDef hdma_uart4_rx; +extern DMA_HandleTypeDef hdma_tim1_up; -extern DMA_HandleTypeDef hdma_uart7_rx; +extern DMA_HandleTypeDef hdma_tim4_up; -extern DMA_HandleTypeDef hdma_uart8_rx; +extern DMA_HandleTypeDef hdma_tim8_up; -extern DMA_HandleTypeDef hdma_usart1_rx; +extern DMA_HandleTypeDef hdma_uart4_rx; -extern DMA_HandleTypeDef hdma_usart3_rx; +extern DMA_HandleTypeDef hdma_usart2_tx; extern DMA_HandleTypeDef hdma_usart6_rx; @@ -727,7 +727,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) HAL_GPIO_Init(SDMMC_CMD_GPIO_Port, &GPIO_InitStruct); /* SDMMC1 interrupt Init */ - HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0); + HAL_NVIC_SetPriority(SDMMC1_IRQn, 1, 0); HAL_NVIC_EnableIRQ(SDMMC1_IRQn); /* USER CODE BEGIN SDMMC1_MspInit 1 */ @@ -1185,6 +1185,29 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); + + /* TIM1 DMA Init */ + /* TIM1_UP Init */ + hdma_tim1_up.Instance = DMA2_Stream6; + hdma_tim1_up.Init.Request = DMA_REQUEST_TIM1_UP; + hdma_tim1_up.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_tim1_up.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_tim1_up.Init.MemInc = DMA_MINC_ENABLE; + hdma_tim1_up.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_tim1_up.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_tim1_up.Init.Mode = DMA_NORMAL; + hdma_tim1_up.Init.Priority = DMA_PRIORITY_LOW; + hdma_tim1_up.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_tim1_up.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_tim1_up.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_tim1_up.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_tim1_up) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_UPDATE],hdma_tim1_up); + /* USER CODE BEGIN TIM1_MspInit 1 */ /* USER CODE END TIM1_MspInit 1 */ @@ -1207,6 +1230,29 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM4_CLK_ENABLE(); + + /* TIM4 DMA Init */ + /* TIM4_UP Init */ + hdma_tim4_up.Instance = DMA2_Stream4; + hdma_tim4_up.Init.Request = DMA_REQUEST_TIM4_UP; + hdma_tim4_up.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_tim4_up.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_tim4_up.Init.MemInc = DMA_MINC_ENABLE; + hdma_tim4_up.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_tim4_up.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_tim4_up.Init.Mode = DMA_NORMAL; + hdma_tim4_up.Init.Priority = DMA_PRIORITY_LOW; + hdma_tim4_up.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_tim4_up.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_tim4_up.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_tim4_up.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_tim4_up) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_UPDATE],hdma_tim4_up); + /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ @@ -1218,6 +1264,29 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM8_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM8_CLK_ENABLE(); + + /* TIM8 DMA Init */ + /* TIM8_UP Init */ + hdma_tim8_up.Instance = DMA2_Stream5; + hdma_tim8_up.Init.Request = DMA_REQUEST_TIM8_UP; + hdma_tim8_up.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_tim8_up.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_tim8_up.Init.MemInc = DMA_MINC_ENABLE; + hdma_tim8_up.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_tim8_up.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_tim8_up.Init.Mode = DMA_NORMAL; + hdma_tim8_up.Init.Priority = DMA_PRIORITY_LOW; + hdma_tim8_up.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_tim8_up.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_tim8_up.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_tim8_up.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_tim8_up) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_UPDATE],hdma_tim8_up); + /* USER CODE BEGIN TIM8_MspInit 1 */ /* USER CODE END TIM8_MspInit 1 */ @@ -1415,6 +1484,9 @@ void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM1_CLK_DISABLE(); + + /* TIM1 DMA DeInit */ + HAL_DMA_DeInit(htim_pwm->hdma[TIM_DMA_ID_UPDATE]); /* USER CODE BEGIN TIM1_MspDeInit 1 */ /* USER CODE END TIM1_MspDeInit 1 */ @@ -1437,6 +1509,9 @@ void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM4_CLK_DISABLE(); + + /* TIM4 DMA DeInit */ + HAL_DMA_DeInit(htim_pwm->hdma[TIM_DMA_ID_UPDATE]); /* USER CODE BEGIN TIM4_MspDeInit 1 */ /* USER CODE END TIM4_MspDeInit 1 */ @@ -1448,6 +1523,9 @@ void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM8_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM8_CLK_DISABLE(); + + /* TIM8 DMA DeInit */ + HAL_DMA_DeInit(htim_pwm->hdma[TIM_DMA_ID_UPDATE]); /* USER CODE BEGIN TIM8_MspDeInit 1 */ /* USER CODE END TIM8_MspDeInit 1 */ @@ -1636,28 +1714,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Alternate = GPIO_AF7_UART7; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - /* UART7 DMA Init */ - /* UART7_RX Init */ - hdma_uart7_rx.Instance = DMA2_Stream0; - hdma_uart7_rx.Init.Request = DMA_REQUEST_UART7_RX; - hdma_uart7_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_uart7_rx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_uart7_rx.Init.MemInc = DMA_MINC_ENABLE; - hdma_uart7_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - hdma_uart7_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - hdma_uart7_rx.Init.Mode = DMA_NORMAL; - hdma_uart7_rx.Init.Priority = DMA_PRIORITY_LOW; - hdma_uart7_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - hdma_uart7_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - hdma_uart7_rx.Init.MemBurst = DMA_MBURST_SINGLE; - hdma_uart7_rx.Init.PeriphBurst = DMA_PBURST_SINGLE; - if (HAL_DMA_Init(&hdma_uart7_rx) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(huart,hdmarx,hdma_uart7_rx); - /* UART7 interrupt Init */ HAL_NVIC_SetPriority(UART7_IRQn, 5, 0); HAL_NVIC_EnableIRQ(UART7_IRQn); @@ -1695,28 +1751,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Alternate = GPIO_AF8_UART8; HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - /* UART8 DMA Init */ - /* UART8_RX Init */ - hdma_uart8_rx.Instance = DMA2_Stream4; - hdma_uart8_rx.Init.Request = DMA_REQUEST_UART8_RX; - hdma_uart8_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_uart8_rx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_uart8_rx.Init.MemInc = DMA_MINC_ENABLE; - hdma_uart8_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - hdma_uart8_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - hdma_uart8_rx.Init.Mode = DMA_NORMAL; - hdma_uart8_rx.Init.Priority = DMA_PRIORITY_LOW; - hdma_uart8_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - hdma_uart8_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - hdma_uart8_rx.Init.MemBurst = DMA_MBURST_SINGLE; - hdma_uart8_rx.Init.PeriphBurst = DMA_PBURST_SINGLE; - if (HAL_DMA_Init(&hdma_uart8_rx) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(huart,hdmarx,hdma_uart8_rx); - /* UART8 interrupt Init */ HAL_NVIC_SetPriority(UART8_IRQn, 5, 0); HAL_NVIC_EnableIRQ(UART8_IRQn); @@ -1761,28 +1795,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Alternate = GPIO_AF7_USART1; HAL_GPIO_Init(FMU_UART1_TX_GPIO_Port, &GPIO_InitStruct); - /* USART1 DMA Init */ - /* USART1_RX Init */ - hdma_usart1_rx.Instance = DMA2_Stream5; - hdma_usart1_rx.Init.Request = DMA_REQUEST_USART1_RX; - hdma_usart1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_usart1_rx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_usart1_rx.Init.MemInc = DMA_MINC_ENABLE; - hdma_usart1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - hdma_usart1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - hdma_usart1_rx.Init.Mode = DMA_NORMAL; - hdma_usart1_rx.Init.Priority = DMA_PRIORITY_LOW; - hdma_usart1_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - hdma_usart1_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - hdma_usart1_rx.Init.MemBurst = DMA_MBURST_SINGLE; - hdma_usart1_rx.Init.PeriphBurst = DMA_PBURST_SINGLE; - if (HAL_DMA_Init(&hdma_usart1_rx) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(huart,hdmarx,hdma_usart1_rx); - /* USART1 interrupt Init */ HAL_NVIC_SetPriority(USART1_IRQn, 5, 0); HAL_NVIC_EnableIRQ(USART1_IRQn); @@ -1829,6 +1841,28 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Alternate = GPIO_AF7_USART2; HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); + /* USART2 DMA Init */ + /* USART2_TX Init */ + hdma_usart2_tx.Instance = DMA2_Stream0; + hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; + hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; + hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + hdma_usart2_tx.Init.Mode = DMA_NORMAL; + hdma_usart2_tx.Init.Priority = DMA_PRIORITY_LOW; + hdma_usart2_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_usart2_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_usart2_tx.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_usart2_tx.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx); + /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 1, 0); HAL_NVIC_EnableIRQ(USART2_IRQn); @@ -1875,28 +1909,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) GPIO_InitStruct.Alternate = GPIO_AF7_USART3; HAL_GPIO_Init(TELEM2_USART3_RX_GPIO_Port, &GPIO_InitStruct); - /* USART3 DMA Init */ - /* USART3_RX Init */ - hdma_usart3_rx.Instance = DMA2_Stream7; - hdma_usart3_rx.Init.Request = DMA_REQUEST_USART3_RX; - hdma_usart3_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_usart3_rx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_usart3_rx.Init.MemInc = DMA_MINC_ENABLE; - hdma_usart3_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - hdma_usart3_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - hdma_usart3_rx.Init.Mode = DMA_NORMAL; - hdma_usart3_rx.Init.Priority = DMA_PRIORITY_LOW; - hdma_usart3_rx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - hdma_usart3_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - hdma_usart3_rx.Init.MemBurst = DMA_MBURST_SINGLE; - hdma_usart3_rx.Init.PeriphBurst = DMA_PBURST_SINGLE; - if (HAL_DMA_Init(&hdma_usart3_rx) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(huart,hdmarx,hdma_usart3_rx); - /* USART3 interrupt Init */ HAL_NVIC_SetPriority(USART3_IRQn, 5, 0); HAL_NVIC_EnableIRQ(USART3_IRQn); @@ -2018,9 +2030,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) */ HAL_GPIO_DeInit(GPIOE, DEBUG_UART7_TX_Pin|DEBUG_UART7_RX_Pin); - /* UART7 DMA DeInit */ - HAL_DMA_DeInit(huart->hdmarx); - /* UART7 interrupt DeInit */ HAL_NVIC_DisableIRQ(UART7_IRQn); /* USER CODE BEGIN UART7_MspDeInit 1 */ @@ -2041,9 +2050,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) */ HAL_GPIO_DeInit(GPIOE, RC_UART8_TX_Pin|RC_UART8_RX_Pin); - /* UART8 DMA DeInit */ - HAL_DMA_DeInit(huart->hdmarx); - /* UART8 interrupt DeInit */ HAL_NVIC_DisableIRQ(UART8_IRQn); /* USER CODE BEGIN UART8_MspDeInit 1 */ @@ -2064,9 +2070,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) */ HAL_GPIO_DeInit(GPIOB, FMU_UART1_RX_Pin|FMU_UART1_TX_Pin); - /* USART1 DMA DeInit */ - HAL_DMA_DeInit(huart->hdmarx); - /* USART1 interrupt DeInit */ HAL_NVIC_DisableIRQ(USART1_IRQn); /* USER CODE BEGIN USART1_MspDeInit 1 */ @@ -2089,6 +2092,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) */ HAL_GPIO_DeInit(GPIOD, TELEM1_USART2_RX_Pin|TELEM1_USART2_TX_Pin|TELEM1_USART2_RTS_Pin|TELEM1_USART2_CTS_Pin); + /* USART2 DMA DeInit */ + HAL_DMA_DeInit(huart->hdmatx); + /* USART2 interrupt DeInit */ HAL_NVIC_DisableIRQ(USART2_IRQn); /* USER CODE BEGIN USART2_MspDeInit 1 */ @@ -2111,9 +2117,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) */ HAL_GPIO_DeInit(GPIOD, TELEM2_USART3_RTS_Pin|TELEM2_USART3_CTS_Pin|TELEM2_USART3_RX_Pin|TELEM2_USART3_TX_Pin); - /* USART3 DMA DeInit */ - HAL_DMA_DeInit(huart->hdmarx); - /* USART3 interrupt DeInit */ HAL_NVIC_DisableIRQ(USART3_IRQn); /* USER CODE BEGIN USART3_MspDeInit 1 */ diff --git a/pixracer_pro/Core/Src/stm32h7xx_it.c b/pixracer_pro/Core/Src/stm32h7xx_it.c index 663cd3e..891b5fb 100644 --- a/pixracer_pro/Core/Src/stm32h7xx_it.c +++ b/pixracer_pro/Core/Src/stm32h7xx_it.c @@ -77,12 +77,12 @@ extern SPI_HandleTypeDef hspi1; extern SPI_HandleTypeDef hspi2; extern SPI_HandleTypeDef hspi5; extern SPI_HandleTypeDef hspi6; +extern DMA_HandleTypeDef hdma_tim1_up; +extern DMA_HandleTypeDef hdma_tim4_up; +extern DMA_HandleTypeDef hdma_tim8_up; extern TIM_HandleTypeDef htim7; extern DMA_HandleTypeDef hdma_uart4_rx; -extern DMA_HandleTypeDef hdma_uart7_rx; -extern DMA_HandleTypeDef hdma_uart8_rx; -extern DMA_HandleTypeDef hdma_usart1_rx; -extern DMA_HandleTypeDef hdma_usart3_rx; +extern DMA_HandleTypeDef hdma_usart2_tx; extern DMA_HandleTypeDef hdma_usart6_rx; extern UART_HandleTypeDef huart4; extern UART_HandleTypeDef huart7; @@ -553,7 +553,7 @@ void DMA2_Stream0_IRQHandler(void) /* USER CODE BEGIN DMA2_Stream0_IRQn 0 */ /* USER CODE END DMA2_Stream0_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_uart7_rx); + HAL_DMA_IRQHandler(&hdma_usart2_tx); /* USER CODE BEGIN DMA2_Stream0_IRQn 1 */ /* USER CODE END DMA2_Stream0_IRQn 1 */ @@ -609,7 +609,7 @@ void DMA2_Stream4_IRQHandler(void) /* USER CODE BEGIN DMA2_Stream4_IRQn 0 */ /* USER CODE END DMA2_Stream4_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_uart8_rx); + HAL_DMA_IRQHandler(&hdma_tim4_up); /* USER CODE BEGIN DMA2_Stream4_IRQn 1 */ /* USER CODE END DMA2_Stream4_IRQn 1 */ @@ -623,24 +623,24 @@ void DMA2_Stream5_IRQHandler(void) /* USER CODE BEGIN DMA2_Stream5_IRQn 0 */ /* USER CODE END DMA2_Stream5_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_usart1_rx); + HAL_DMA_IRQHandler(&hdma_tim8_up); /* USER CODE BEGIN DMA2_Stream5_IRQn 1 */ /* USER CODE END DMA2_Stream5_IRQn 1 */ } /** - * @brief This function handles DMA2 stream7 global interrupt. + * @brief This function handles DMA2 stream6 global interrupt. */ -void DMA2_Stream7_IRQHandler(void) +void DMA2_Stream6_IRQHandler(void) { - /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ + /* USER CODE BEGIN DMA2_Stream6_IRQn 0 */ - /* USER CODE END DMA2_Stream7_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_usart3_rx); - /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ + /* USER CODE END DMA2_Stream6_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_tim1_up); + /* USER CODE BEGIN DMA2_Stream6_IRQn 1 */ - /* USER CODE END DMA2_Stream7_IRQn 1 */ + /* USER CODE END DMA2_Stream6_IRQn 1 */ } /** diff --git a/pixracer_pro/pixracer_pro.ioc b/pixracer_pro/pixracer_pro.ioc index 5b7ea09..700032a 100644 --- a/pixracer_pro/pixracer_pro.ioc +++ b/pixracer_pro/pixracer_pro.ioc @@ -189,10 +189,10 @@ Dma.I2C1_TX.10.SyncSignalID=NONE Dma.Request0=ADC1 Dma.Request1=SPI1_RX Dma.Request10=I2C1_TX -Dma.Request11=UART8_RX -Dma.Request12=USART1_RX -Dma.Request13=USART3_RX -Dma.Request14=UART7_RX +Dma.Request11=TIM1_UP +Dma.Request12=USART2_TX +Dma.Request13=TIM8_UP +Dma.Request14=TIM4_UP Dma.Request2=SPI1_TX Dma.Request3=SPI2_RX Dma.Request4=SPI2_TX @@ -325,6 +325,69 @@ Dma.SPI5_TX.6.SyncEnable=DISABLE Dma.SPI5_TX.6.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.SPI5_TX.6.SyncRequestNumber=1 Dma.SPI5_TX.6.SyncSignalID=NONE +Dma.TIM1_UP.11.Direction=DMA_MEMORY_TO_PERIPH +Dma.TIM1_UP.11.EventEnable=DISABLE +Dma.TIM1_UP.11.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.TIM1_UP.11.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.TIM1_UP.11.Instance=DMA2_Stream6 +Dma.TIM1_UP.11.MemBurst=DMA_MBURST_SINGLE +Dma.TIM1_UP.11.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.TIM1_UP.11.MemInc=DMA_MINC_ENABLE +Dma.TIM1_UP.11.Mode=DMA_NORMAL +Dma.TIM1_UP.11.PeriphBurst=DMA_PBURST_SINGLE +Dma.TIM1_UP.11.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.TIM1_UP.11.PeriphInc=DMA_PINC_DISABLE +Dma.TIM1_UP.11.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.TIM1_UP.11.Priority=DMA_PRIORITY_LOW +Dma.TIM1_UP.11.RequestNumber=1 +Dma.TIM1_UP.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.TIM1_UP.11.SignalID=NONE +Dma.TIM1_UP.11.SyncEnable=DISABLE +Dma.TIM1_UP.11.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.TIM1_UP.11.SyncRequestNumber=1 +Dma.TIM1_UP.11.SyncSignalID=NONE +Dma.TIM4_UP.14.Direction=DMA_MEMORY_TO_PERIPH +Dma.TIM4_UP.14.EventEnable=DISABLE +Dma.TIM4_UP.14.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.TIM4_UP.14.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.TIM4_UP.14.Instance=DMA2_Stream4 +Dma.TIM4_UP.14.MemBurst=DMA_MBURST_SINGLE +Dma.TIM4_UP.14.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.TIM4_UP.14.MemInc=DMA_MINC_ENABLE +Dma.TIM4_UP.14.Mode=DMA_NORMAL +Dma.TIM4_UP.14.PeriphBurst=DMA_PBURST_SINGLE +Dma.TIM4_UP.14.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.TIM4_UP.14.PeriphInc=DMA_PINC_DISABLE +Dma.TIM4_UP.14.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.TIM4_UP.14.Priority=DMA_PRIORITY_LOW +Dma.TIM4_UP.14.RequestNumber=1 +Dma.TIM4_UP.14.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.TIM4_UP.14.SignalID=NONE +Dma.TIM4_UP.14.SyncEnable=DISABLE +Dma.TIM4_UP.14.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.TIM4_UP.14.SyncRequestNumber=1 +Dma.TIM4_UP.14.SyncSignalID=NONE +Dma.TIM8_UP.13.Direction=DMA_MEMORY_TO_PERIPH +Dma.TIM8_UP.13.EventEnable=DISABLE +Dma.TIM8_UP.13.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.TIM8_UP.13.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.TIM8_UP.13.Instance=DMA2_Stream5 +Dma.TIM8_UP.13.MemBurst=DMA_MBURST_SINGLE +Dma.TIM8_UP.13.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.TIM8_UP.13.MemInc=DMA_MINC_ENABLE +Dma.TIM8_UP.13.Mode=DMA_NORMAL +Dma.TIM8_UP.13.PeriphBurst=DMA_PBURST_SINGLE +Dma.TIM8_UP.13.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.TIM8_UP.13.PeriphInc=DMA_PINC_DISABLE +Dma.TIM8_UP.13.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.TIM8_UP.13.Priority=DMA_PRIORITY_LOW +Dma.TIM8_UP.13.RequestNumber=1 +Dma.TIM8_UP.13.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.TIM8_UP.13.SignalID=NONE +Dma.TIM8_UP.13.SyncEnable=DISABLE +Dma.TIM8_UP.13.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.TIM8_UP.13.SyncRequestNumber=1 +Dma.TIM8_UP.13.SyncSignalID=NONE Dma.UART4_RX.7.Direction=DMA_PERIPH_TO_MEMORY Dma.UART4_RX.7.EventEnable=DISABLE Dma.UART4_RX.7.FIFOMode=DMA_FIFOMODE_ENABLE @@ -346,90 +409,27 @@ Dma.UART4_RX.7.SyncEnable=DISABLE Dma.UART4_RX.7.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.UART4_RX.7.SyncRequestNumber=1 Dma.UART4_RX.7.SyncSignalID=NONE -Dma.UART7_RX.14.Direction=DMA_PERIPH_TO_MEMORY -Dma.UART7_RX.14.EventEnable=DISABLE -Dma.UART7_RX.14.FIFOMode=DMA_FIFOMODE_ENABLE -Dma.UART7_RX.14.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL -Dma.UART7_RX.14.Instance=DMA2_Stream0 -Dma.UART7_RX.14.MemBurst=DMA_MBURST_SINGLE -Dma.UART7_RX.14.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.UART7_RX.14.MemInc=DMA_MINC_ENABLE -Dma.UART7_RX.14.Mode=DMA_NORMAL -Dma.UART7_RX.14.PeriphBurst=DMA_PBURST_SINGLE -Dma.UART7_RX.14.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.UART7_RX.14.PeriphInc=DMA_PINC_DISABLE -Dma.UART7_RX.14.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.UART7_RX.14.Priority=DMA_PRIORITY_LOW -Dma.UART7_RX.14.RequestNumber=1 -Dma.UART7_RX.14.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.UART7_RX.14.SignalID=NONE -Dma.UART7_RX.14.SyncEnable=DISABLE -Dma.UART7_RX.14.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.UART7_RX.14.SyncRequestNumber=1 -Dma.UART7_RX.14.SyncSignalID=NONE -Dma.UART8_RX.11.Direction=DMA_PERIPH_TO_MEMORY -Dma.UART8_RX.11.EventEnable=DISABLE -Dma.UART8_RX.11.FIFOMode=DMA_FIFOMODE_ENABLE -Dma.UART8_RX.11.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL -Dma.UART8_RX.11.Instance=DMA2_Stream4 -Dma.UART8_RX.11.MemBurst=DMA_MBURST_SINGLE -Dma.UART8_RX.11.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.UART8_RX.11.MemInc=DMA_MINC_ENABLE -Dma.UART8_RX.11.Mode=DMA_NORMAL -Dma.UART8_RX.11.PeriphBurst=DMA_PBURST_SINGLE -Dma.UART8_RX.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.UART8_RX.11.PeriphInc=DMA_PINC_DISABLE -Dma.UART8_RX.11.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.UART8_RX.11.Priority=DMA_PRIORITY_LOW -Dma.UART8_RX.11.RequestNumber=1 -Dma.UART8_RX.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.UART8_RX.11.SignalID=NONE -Dma.UART8_RX.11.SyncEnable=DISABLE -Dma.UART8_RX.11.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.UART8_RX.11.SyncRequestNumber=1 -Dma.UART8_RX.11.SyncSignalID=NONE -Dma.USART1_RX.12.Direction=DMA_PERIPH_TO_MEMORY -Dma.USART1_RX.12.EventEnable=DISABLE -Dma.USART1_RX.12.FIFOMode=DMA_FIFOMODE_ENABLE -Dma.USART1_RX.12.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL -Dma.USART1_RX.12.Instance=DMA2_Stream5 -Dma.USART1_RX.12.MemBurst=DMA_MBURST_SINGLE -Dma.USART1_RX.12.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.USART1_RX.12.MemInc=DMA_MINC_ENABLE -Dma.USART1_RX.12.Mode=DMA_NORMAL -Dma.USART1_RX.12.PeriphBurst=DMA_PBURST_SINGLE -Dma.USART1_RX.12.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.USART1_RX.12.PeriphInc=DMA_PINC_DISABLE -Dma.USART1_RX.12.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.USART1_RX.12.Priority=DMA_PRIORITY_LOW -Dma.USART1_RX.12.RequestNumber=1 -Dma.USART1_RX.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.USART1_RX.12.SignalID=NONE -Dma.USART1_RX.12.SyncEnable=DISABLE -Dma.USART1_RX.12.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.USART1_RX.12.SyncRequestNumber=1 -Dma.USART1_RX.12.SyncSignalID=NONE -Dma.USART3_RX.13.Direction=DMA_PERIPH_TO_MEMORY -Dma.USART3_RX.13.EventEnable=DISABLE -Dma.USART3_RX.13.FIFOMode=DMA_FIFOMODE_ENABLE -Dma.USART3_RX.13.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL -Dma.USART3_RX.13.Instance=DMA2_Stream7 -Dma.USART3_RX.13.MemBurst=DMA_MBURST_SINGLE -Dma.USART3_RX.13.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.USART3_RX.13.MemInc=DMA_MINC_ENABLE -Dma.USART3_RX.13.Mode=DMA_NORMAL -Dma.USART3_RX.13.PeriphBurst=DMA_PBURST_SINGLE -Dma.USART3_RX.13.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.USART3_RX.13.PeriphInc=DMA_PINC_DISABLE -Dma.USART3_RX.13.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.USART3_RX.13.Priority=DMA_PRIORITY_LOW -Dma.USART3_RX.13.RequestNumber=1 -Dma.USART3_RX.13.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.USART3_RX.13.SignalID=NONE -Dma.USART3_RX.13.SyncEnable=DISABLE -Dma.USART3_RX.13.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.USART3_RX.13.SyncRequestNumber=1 -Dma.USART3_RX.13.SyncSignalID=NONE +Dma.USART2_TX.12.Direction=DMA_MEMORY_TO_PERIPH +Dma.USART2_TX.12.EventEnable=DISABLE +Dma.USART2_TX.12.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.USART2_TX.12.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.USART2_TX.12.Instance=DMA2_Stream0 +Dma.USART2_TX.12.MemBurst=DMA_MBURST_SINGLE +Dma.USART2_TX.12.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART2_TX.12.MemInc=DMA_MINC_ENABLE +Dma.USART2_TX.12.Mode=DMA_NORMAL +Dma.USART2_TX.12.PeriphBurst=DMA_PBURST_SINGLE +Dma.USART2_TX.12.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART2_TX.12.PeriphInc=DMA_PINC_DISABLE +Dma.USART2_TX.12.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.USART2_TX.12.Priority=DMA_PRIORITY_LOW +Dma.USART2_TX.12.RequestNumber=1 +Dma.USART2_TX.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.USART2_TX.12.SignalID=NONE +Dma.USART2_TX.12.SyncEnable=DISABLE +Dma.USART2_TX.12.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.USART2_TX.12.SyncRequestNumber=1 +Dma.USART2_TX.12.SyncSignalID=NONE Dma.USART6_RX.8.Direction=DMA_PERIPH_TO_MEMORY Dma.USART6_RX.8.EventEnable=DISABLE Dma.USART6_RX.8.FIFOMode=DMA_FIFOMODE_ENABLE @@ -627,9 +627,9 @@ NVIC.DMA2_Stream0_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA2_Stream1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA2_Stream2_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA2_Stream3_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA2_Stream4_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA2_Stream4_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true NVIC.DMA2_Stream5_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA2_Stream7_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA2_Stream6_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.EXTI15_10_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.EXTI1_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true @@ -643,7 +643,7 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.OTG_FS_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SDMMC1_IRQn=true\:2\:0\:true\:false\:true\:true\:true\:true +NVIC.SDMMC1_IRQn=true\:1\:0\:true\:false\:true\:true\:true\:true NVIC.SPI1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.SPI2_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.SPI5_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true diff --git a/pixracer_pro/specific/BoardConfig.h b/pixracer_pro/specific/BoardConfig.h index 53d253b..937f65a 100644 --- a/pixracer_pro/specific/BoardConfig.h +++ b/pixracer_pro/specific/BoardConfig.h @@ -94,38 +94,37 @@ extern PCD_HandleTypeDef hpcd_USB_OTG_FS; // USB FS (48 MB/s) #define POLLING_FREQ_HZ (1000000 / POLLING_PERIOD_US) // 10000 Hz // Pwm's -#define PWM_MIN (1000) -#define PWM_CENTER (1500) -#define PWM_MAX (2000) - -// TIMER, CHAN, PWM_STD|PWM_DSHOT, 50|300|600, ... -// for PWM_STD, Hz, for DSHOT, bps -// PWM_STD or PWM_DSHOT -#define PWM_DSHOT_PERIOD_COUNTS (667) // 300000 bps 667 counts per bit at 200MHz clock -#define PWM_MKS_PERIOD_COUNTS (3000) // 333Hz at 1MHz clock -#define PWM_STD_PERIOD_COUNTS (20000) // 50 Hz at 1MHz clock - -#define PWM_BLOCKS 3 -#define PWM_BLOCKS_DEFINE \ -{ \ - { TIM1, PWM_STD, PWM_STD_PERIOD_COUNTS}, \ - { TIM4, PWM_STD, PWM_STD_PERIOD_COUNTS}, \ - { TIM8, PWM_STD, PWM_STD_PERIOD_COUNTS} \ -} +//#define PWM_SERVO_MIN (1000) +//#define PWM_SERVO_MAX (2000) +// +//#define DSHOT_ESC_MIN (48) +//#define DSHOT_ESC_MAX (2047) +// +//#define PWM_DSHOT_RATE_HZ (300000.0) // baud rate +//#define PWM_MKS_RATE_HZ (333.0) +//#define PWM_STD_RATE_HZ (50.0) #define PWM_CHANNELS (8) // Number of PWM output channels on the board -#define PWM_CHANNELS_DEFINE \ +#define PWM_TIMER_BLOCKS 3 + +//typedef enum : uint8_t +//{ +// PWM_STANDARD, +// PWM_DSHOT +//} pwm_type; + +// Arrays are the mapping of CH1-4 to the 10 PWM Channels Index +#define PWM_INIT_DEFINE \ { \ - { (&htim1), TIM_CHANNEL_4, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim1), TIM_CHANNEL_3, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim1), TIM_CHANNEL_2, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim1), TIM_CHANNEL_1, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim4), TIM_CHANNEL_2, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim4), TIM_CHANNEL_3, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim8), TIM_CHANNEL_1, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim8), TIM_CHANNEL_2, PWM_MIN, PWM_CENTER, PWM_MAX} \ + { (&htim1), PWM_STANDARD, PWM_STD_RATE_HZ, { 3, 2, 1, 0}}, \ + { (&htim4), PWM_STANDARD, PWM_STD_RATE_HZ, { 255, 4, 5, 255}}, \ + { (&htim3), PWM_STANDARD, PWM_STD_RATE_HZ, { 6, 7, 255, 255}} \ } +// Channel order based on hardware pinout naming +// TIMER 1 TIM_CHANNEL_4, TIM_CHANNEL_3, TIM_CHANNEL_2, TIM_CHANNEL_1 +// TIMER 4 TIM_CHANNEL_2, TIM_CHANNEL_3 +// TIMER 3 TIM_CHANNEL_1, TIM_CHANNEL_2 // BMI088 IMU diff --git a/pixracer_pro/specific/Varmint.h b/pixracer_pro/specific/Varmint.h index 5f7c363..c8d1b52 100644 --- a/pixracer_pro/specific/Varmint.h +++ b/pixracer_pro/specific/Varmint.h @@ -148,8 +148,10 @@ class Varmint : public rosflight_firmware::Board // PWM void pwm_init(uint32_t refresh_rate, uint16_t idle_pwm) override; + void pwm_init(const float *rate, uint32_t channels) override; void pwm_disable() override; void pwm_write(uint8_t channel, float value) override; + void pwm_write(float *value, uint32_t channels) override; uint32_t pwm_init_timers(uint32_t servo_pwm_period_us); // non-volatile memory diff --git a/test/board.h b/test/board.h index d2f132f..91808ae 100644 --- a/test/board.h +++ b/test/board.h @@ -85,10 +85,7 @@ struct GNSSData uint64_t rosflight_timestamp; // microseconds, time stamp of last byte in the message - GNSSData() - { - memset(this, 0, sizeof(GNSSData)); - } + GNSSData() { memset(this, 0, sizeof(GNSSData)); } }; struct GNSSFull @@ -121,10 +118,7 @@ struct GNSSFull uint16_t p_dop; uint64_t rosflight_timestamp; // microseconds, time stamp of last byte in the message - GNSSFull() - { - memset(this, 0, sizeof(GNSSFull)); - } + GNSSFull() { memset(this, 0, sizeof(GNSSFull)); } }; class Board diff --git a/varmint_10X/.settings/language.settings.xml b/varmint_10X/.settings/language.settings.xml index ccd4fca..db00d30 100644 --- a/varmint_10X/.settings/language.settings.xml +++ b/varmint_10X/.settings/language.settings.xml @@ -5,7 +5,7 @@ - + @@ -16,7 +16,7 @@ - + diff --git a/varmint_10X/Core/Inc/stm32h7xx_hal_conf.h b/varmint_10X/Core/Inc/stm32h7xx_hal_conf.h index 8f380eb..b349999 100644 --- a/varmint_10X/Core/Inc/stm32h7xx_hal_conf.h +++ b/varmint_10X/Core/Inc/stm32h7xx_hal_conf.h @@ -166,7 +166,7 @@ * @brief This is the HAL system configuration section */ #define VDD_VALUE (3300UL) /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority */ +#define TICK_INT_PRIORITY (0UL) /*!< tick interrupt priority */ #define USE_RTOS 0 #define USE_SD_TRANSCEIVER 0U /*!< use uSD Transceiver */ #define USE_SPI_CRC 0U /*!< use CRC in SPI */ diff --git a/varmint_10X/Core/Src/main.c b/varmint_10X/Core/Src/main.c index 35b72c6..dd3e709 100644 --- a/varmint_10X/Core/Src/main.c +++ b/varmint_10X/Core/Src/main.c @@ -79,15 +79,15 @@ TIM_HandleTypeDef htim5; TIM_HandleTypeDef htim7; TIM_HandleTypeDef htim8; TIM_HandleTypeDef htim12; +DMA_HandleTypeDef hdma_tim1_up; +DMA_HandleTypeDef hdma_tim4_up; UART_HandleTypeDef huart1; UART_HandleTypeDef huart2; UART_HandleTypeDef huart3; DMA_HandleTypeDef hdma_usart1_rx; DMA_HandleTypeDef hdma_usart2_tx; -DMA_HandleTypeDef hdma_usart2_rx; DMA_HandleTypeDef hdma_usart3_rx; -DMA_HandleTypeDef hdma_usart3_tx; PCD_HandleTypeDef hpcd_USB_OTG_FS; @@ -1589,10 +1589,10 @@ void MX_DMA_Init(void) HAL_NVIC_SetPriority(DMA2_Stream5_IRQn, 5, 0); HAL_NVIC_EnableIRQ(DMA2_Stream5_IRQn); /* DMA2_Stream6_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA2_Stream6_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA2_Stream6_IRQn); /* DMA2_Stream7_IRQn interrupt configuration */ - HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 5, 0); + HAL_NVIC_SetPriority(DMA2_Stream7_IRQn, 0, 0); HAL_NVIC_EnableIRQ(DMA2_Stream7_IRQn); } diff --git a/varmint_10X/Core/Src/stm32h7xx_hal_msp.c b/varmint_10X/Core/Src/stm32h7xx_hal_msp.c index 0949fd9..0b995af 100644 --- a/varmint_10X/Core/Src/stm32h7xx_hal_msp.c +++ b/varmint_10X/Core/Src/stm32h7xx_hal_msp.c @@ -47,16 +47,16 @@ extern DMA_HandleTypeDef hdma_spi4_rx; extern DMA_HandleTypeDef hdma_spi4_tx; +extern DMA_HandleTypeDef hdma_tim1_up; + +extern DMA_HandleTypeDef hdma_tim4_up; + extern DMA_HandleTypeDef hdma_usart1_rx; extern DMA_HandleTypeDef hdma_usart2_tx; -extern DMA_HandleTypeDef hdma_usart2_rx; - extern DMA_HandleTypeDef hdma_usart3_rx; -extern DMA_HandleTypeDef hdma_usart3_tx; - /* Private typedef -----------------------------------------------------------*/ /* USER CODE BEGIN TD */ @@ -730,7 +730,7 @@ void HAL_SD_MspInit(SD_HandleTypeDef* hsd) HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); /* SDMMC1 interrupt Init */ - HAL_NVIC_SetPriority(SDMMC1_IRQn, 2, 0); + HAL_NVIC_SetPriority(SDMMC1_IRQn, 1, 0); HAL_NVIC_EnableIRQ(SDMMC1_IRQn); /* USER CODE BEGIN SDMMC1_MspInit 1 */ @@ -1228,6 +1228,29 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); + + /* TIM1 DMA Init */ + /* TIM1_UP Init */ + hdma_tim1_up.Instance = DMA2_Stream6; + hdma_tim1_up.Init.Request = DMA_REQUEST_TIM1_UP; + hdma_tim1_up.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_tim1_up.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_tim1_up.Init.MemInc = DMA_MINC_ENABLE; + hdma_tim1_up.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_tim1_up.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_tim1_up.Init.Mode = DMA_NORMAL; + hdma_tim1_up.Init.Priority = DMA_PRIORITY_LOW; + hdma_tim1_up.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_tim1_up.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_tim1_up.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_tim1_up.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_tim1_up) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_UPDATE],hdma_tim1_up); + /* USER CODE BEGIN TIM1_MspInit 1 */ /* USER CODE END TIM1_MspInit 1 */ @@ -1250,6 +1273,29 @@ void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM4_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM4_CLK_ENABLE(); + + /* TIM4 DMA Init */ + /* TIM4_UP Init */ + hdma_tim4_up.Instance = DMA2_Stream7; + hdma_tim4_up.Init.Request = DMA_REQUEST_TIM4_UP; + hdma_tim4_up.Init.Direction = DMA_MEMORY_TO_PERIPH; + hdma_tim4_up.Init.PeriphInc = DMA_PINC_DISABLE; + hdma_tim4_up.Init.MemInc = DMA_MINC_ENABLE; + hdma_tim4_up.Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD; + hdma_tim4_up.Init.MemDataAlignment = DMA_MDATAALIGN_WORD; + hdma_tim4_up.Init.Mode = DMA_NORMAL; + hdma_tim4_up.Init.Priority = DMA_PRIORITY_LOW; + hdma_tim4_up.Init.FIFOMode = DMA_FIFOMODE_ENABLE; + hdma_tim4_up.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; + hdma_tim4_up.Init.MemBurst = DMA_MBURST_SINGLE; + hdma_tim4_up.Init.PeriphBurst = DMA_PBURST_SINGLE; + if (HAL_DMA_Init(&hdma_tim4_up) != HAL_OK) + { + Error_Handler(); + } + + __HAL_LINKDMA(htim_pwm,hdma[TIM_DMA_ID_UPDATE],hdma_tim4_up); + /* USER CODE BEGIN TIM4_MspInit 1 */ /* USER CODE END TIM4_MspInit 1 */ @@ -1441,6 +1487,9 @@ void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM1_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM1_CLK_DISABLE(); + + /* TIM1 DMA DeInit */ + HAL_DMA_DeInit(htim_pwm->hdma[TIM_DMA_ID_UPDATE]); /* USER CODE BEGIN TIM1_MspDeInit 1 */ /* USER CODE END TIM1_MspDeInit 1 */ @@ -1463,6 +1512,9 @@ void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef* htim_pwm) /* USER CODE END TIM4_MspDeInit 0 */ /* Peripheral clock disable */ __HAL_RCC_TIM4_CLK_DISABLE(); + + /* TIM4 DMA DeInit */ + HAL_DMA_DeInit(htim_pwm->hdma[TIM_DMA_ID_UPDATE]); /* USER CODE BEGIN TIM4_MspDeInit 1 */ /* USER CODE END TIM4_MspDeInit 1 */ @@ -1663,24 +1715,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx); - /* USART2_RX Init */ - hdma_usart2_rx.Instance = DMA2_Stream6; - hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX; - hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; - hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; - hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - hdma_usart2_rx.Init.Mode = DMA_NORMAL; - hdma_usart2_rx.Init.Priority = DMA_PRIORITY_LOW; - hdma_usart2_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE; - if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx); - /* USART2 interrupt Init */ HAL_NVIC_SetPriority(USART2_IRQn, 1, 0); HAL_NVIC_EnableIRQ(USART2_IRQn); @@ -1747,27 +1781,6 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart) __HAL_LINKDMA(huart,hdmarx,hdma_usart3_rx); - /* USART3_TX Init */ - hdma_usart3_tx.Instance = DMA2_Stream7; - hdma_usart3_tx.Init.Request = DMA_REQUEST_USART3_TX; - hdma_usart3_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; - hdma_usart3_tx.Init.PeriphInc = DMA_PINC_DISABLE; - hdma_usart3_tx.Init.MemInc = DMA_MINC_ENABLE; - hdma_usart3_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; - hdma_usart3_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; - hdma_usart3_tx.Init.Mode = DMA_NORMAL; - hdma_usart3_tx.Init.Priority = DMA_PRIORITY_LOW; - hdma_usart3_tx.Init.FIFOMode = DMA_FIFOMODE_ENABLE; - hdma_usart3_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL; - hdma_usart3_tx.Init.MemBurst = DMA_MBURST_SINGLE; - hdma_usart3_tx.Init.PeriphBurst = DMA_PBURST_SINGLE; - if (HAL_DMA_Init(&hdma_usart3_tx) != HAL_OK) - { - Error_Handler(); - } - - __HAL_LINKDMA(huart,hdmatx,hdma_usart3_tx); - /* USART3 interrupt Init */ HAL_NVIC_SetPriority(USART3_IRQn, 5, 0); HAL_NVIC_EnableIRQ(USART3_IRQn); @@ -1829,7 +1842,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USART2 DMA DeInit */ HAL_DMA_DeInit(huart->hdmatx); - HAL_DMA_DeInit(huart->hdmarx); /* USART2 interrupt DeInit */ HAL_NVIC_DisableIRQ(USART2_IRQn); @@ -1853,7 +1865,6 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) /* USART3 DMA DeInit */ HAL_DMA_DeInit(huart->hdmarx); - HAL_DMA_DeInit(huart->hdmatx); /* USART3 interrupt DeInit */ HAL_NVIC_DisableIRQ(USART3_IRQn); diff --git a/varmint_10X/Core/Src/stm32h7xx_it.c b/varmint_10X/Core/Src/stm32h7xx_it.c index 5c24950..d6b7e44 100644 --- a/varmint_10X/Core/Src/stm32h7xx_it.c +++ b/varmint_10X/Core/Src/stm32h7xx_it.c @@ -76,12 +76,12 @@ extern SPI_HandleTypeDef hspi1; extern SPI_HandleTypeDef hspi2; extern SPI_HandleTypeDef hspi3; extern SPI_HandleTypeDef hspi4; +extern DMA_HandleTypeDef hdma_tim1_up; +extern DMA_HandleTypeDef hdma_tim4_up; extern TIM_HandleTypeDef htim7; extern DMA_HandleTypeDef hdma_usart1_rx; extern DMA_HandleTypeDef hdma_usart2_tx; -extern DMA_HandleTypeDef hdma_usart2_rx; extern DMA_HandleTypeDef hdma_usart3_rx; -extern DMA_HandleTypeDef hdma_usart3_tx; extern UART_HandleTypeDef huart1; extern UART_HandleTypeDef huart2; extern UART_HandleTypeDef huart3; @@ -696,7 +696,7 @@ void DMA2_Stream6_IRQHandler(void) /* USER CODE BEGIN DMA2_Stream6_IRQn 0 */ /* USER CODE END DMA2_Stream6_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_usart2_rx); + HAL_DMA_IRQHandler(&hdma_tim1_up); /* USER CODE BEGIN DMA2_Stream6_IRQn 1 */ /* USER CODE END DMA2_Stream6_IRQn 1 */ @@ -710,7 +710,7 @@ void DMA2_Stream7_IRQHandler(void) /* USER CODE BEGIN DMA2_Stream7_IRQn 0 */ /* USER CODE END DMA2_Stream7_IRQn 0 */ - HAL_DMA_IRQHandler(&hdma_usart3_tx); + HAL_DMA_IRQHandler(&hdma_tim4_up); /* USER CODE BEGIN DMA2_Stream7_IRQn 1 */ /* USER CODE END DMA2_Stream7_IRQn 1 */ diff --git a/varmint_10X/specific/BoardConfig.h b/varmint_10X/specific/BoardConfig.h index b0ad4b1..a5876b0 100644 --- a/varmint_10X/specific/BoardConfig.h +++ b/varmint_10X/specific/BoardConfig.h @@ -93,41 +93,40 @@ extern PCD_HandleTypeDef hpcd_USB_OTG_FS; // USB FS (48 MB/s) #define POLLING_PERIOD_US (100) // 100us, 10kHz #define POLLING_FREQ_HZ (1000000 / POLLING_PERIOD_US) // 10000 Hz +/////////////////////////////////////////////////////////////////////////////////////////////////// // Pwm's -#define PWM_MIN (1000) -#define PWM_CENTER (1500) -#define PWM_MAX (2000) - -// TIMER, CHAN, PWM_STD|PWM_DSHOT, 50|300|600, ... -// for PWM_STD, Hz, for DSHOT, bps -// PWM_STD or PWM_DSHOT -#define PWM_DSHOT_PERIOD_COUNTS (667) // 300000 bps 667 counts per bit at 200MHz clock -#define PWM_MKS_PERIOD_COUNTS (3000) // 333Hz at 1MHz clock -#define PWM_STD_PERIOD_COUNTS (20000) // 50 Hz at 1MHz clock - -#define PWM_BLOCKS 3 -#define PWM_BLOCKS_DEFINE \ -{ \ - { TIM1, PWM_STD, PWM_STD_PERIOD_COUNTS}, \ - { TIM4, PWM_STD, PWM_STD_PERIOD_COUNTS}, \ - { TIM3, PWM_STD, PWM_STD_PERIOD_COUNTS} \ -} +//#define PWM_SERVO_MIN (1000) +//#define PWM_SERVO_MAX (2000) +// +//#define DSHOT_ESC_MIN (48) +//#define DSHOT_ESC_MAX (2047) +// +//#define PWM_DSHOT_RATE_HZ (300000.0) // baud rate +//#define PWM_MKS_RATE_HZ (333.0) +//#define PWM_STD_RATE_HZ (50.0) -#define PWM_CHANNELS (10) // Number of PWM output channels on the board -#define PWM_CHANNELS_DEFINE \ +#define PWM_CHANNELS (10) // Number of PWM output channels on the board +#define PWM_TIMER_BLOCKS (3) + +//typedef enum : uint8_t +//{ +// PWM_STANDARD, +// PWM_DSHOT +//} pwm_type; + +// Arrays are the mapping of CH1-4 to the 10 PWM Channels Index +#define PWM_INIT_DEFINE \ { \ - { (&htim1), TIM_CHANNEL_1, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim1), TIM_CHANNEL_2, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim1), TIM_CHANNEL_3, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim1), TIM_CHANNEL_4, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim4), TIM_CHANNEL_3, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim4), TIM_CHANNEL_2, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim4), TIM_CHANNEL_1, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim4), TIM_CHANNEL_4, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim3), TIM_CHANNEL_1, PWM_MIN, PWM_CENTER, PWM_MAX}, \ - { (&htim3), TIM_CHANNEL_2, PWM_MIN, PWM_CENTER, PWM_MAX} \ + { (&htim1), PWM_STANDARD, PWM_STD_RATE_HZ, { 0, 1, 2, 3}}, \ + { (&htim4), PWM_STANDARD, PWM_STD_RATE_HZ, { 6, 5, 4, 7}}, \ + { (&htim3), PWM_STANDARD, PWM_STD_RATE_HZ, { 8, 9, 255, 255}} \ } +// Channel order based on hardware pinout naming +// TIMER 1 TIM_CHANNEL_1, TIM_CHANNEL_2, TIM_CHANNEL_3, TIM_CHANNEL_4, +// TIMER 4 TIM_CHANNEL_3, TIM_CHANNEL_2, TIM_CHANNEL_1, TIM_CHANNEL_4, +// TIMER 3 TIM_CHANNEL_1, TIM_CHANNEL_2 + // BMI088 IMU #define BMI088_SPI (&hspi1) diff --git a/varmint_10X/specific/Varmint.h b/varmint_10X/specific/Varmint.h index 667e377..6af0eb3 100644 --- a/varmint_10X/specific/Varmint.h +++ b/varmint_10X/specific/Varmint.h @@ -149,8 +149,10 @@ class Varmint : public rosflight_firmware::Board // PWM void pwm_init(uint32_t refresh_rate, uint16_t idle_pwm) override; + void pwm_init(const float *rate, uint32_t channels) override; void pwm_disable() override; void pwm_write(uint8_t channel, float value) override; + void pwm_write(float *value, uint32_t channels) override; uint32_t pwm_init_timers(uint32_t servo_pwm_period_us); // non-volatile memory diff --git a/varmint_10X/varmint_10X.ioc b/varmint_10X/varmint_10X.ioc index 5142a56..0dc3d03 100644 --- a/varmint_10X/varmint_10X.ioc +++ b/varmint_10X/varmint_10X.ioc @@ -105,77 +105,77 @@ CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region0_Settings=MPU_REGION_SIZE_32 CORTEX_M7.Size-Cortex_Memory_Protection_Unit_Region1_Settings=MPU_REGION_SIZE_64KB CORTEX_M7.SubRegionDisable-Cortex_Memory_Protection_Unit_Region0_Settings=0x00 CORTEX_M7.default_mode_Activation=0 -Dma.ADC1.13.Direction=DMA_PERIPH_TO_MEMORY -Dma.ADC1.13.EventEnable=DISABLE -Dma.ADC1.13.FIFOMode=DMA_FIFOMODE_ENABLE -Dma.ADC1.13.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL -Dma.ADC1.13.Instance=DMA2_Stream0 -Dma.ADC1.13.MemBurst=DMA_MBURST_SINGLE -Dma.ADC1.13.MemDataAlignment=DMA_MDATAALIGN_WORD -Dma.ADC1.13.MemInc=DMA_MINC_ENABLE -Dma.ADC1.13.Mode=DMA_NORMAL -Dma.ADC1.13.PeriphBurst=DMA_PBURST_SINGLE -Dma.ADC1.13.PeriphDataAlignment=DMA_PDATAALIGN_WORD -Dma.ADC1.13.PeriphInc=DMA_PINC_DISABLE -Dma.ADC1.13.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.ADC1.13.Priority=DMA_PRIORITY_LOW -Dma.ADC1.13.RequestNumber=1 -Dma.ADC1.13.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.ADC1.13.SignalID=NONE -Dma.ADC1.13.SyncEnable=DISABLE -Dma.ADC1.13.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.ADC1.13.SyncRequestNumber=1 -Dma.ADC1.13.SyncSignalID=NONE -Dma.I2C1_RX.11.Direction=DMA_PERIPH_TO_MEMORY -Dma.I2C1_RX.11.EventEnable=DISABLE -Dma.I2C1_RX.11.FIFOMode=DMA_FIFOMODE_ENABLE -Dma.I2C1_RX.11.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL -Dma.I2C1_RX.11.Instance=DMA1_Stream0 -Dma.I2C1_RX.11.MemBurst=DMA_MBURST_SINGLE -Dma.I2C1_RX.11.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.I2C1_RX.11.MemInc=DMA_MINC_ENABLE -Dma.I2C1_RX.11.Mode=DMA_NORMAL -Dma.I2C1_RX.11.PeriphBurst=DMA_PBURST_SINGLE -Dma.I2C1_RX.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.I2C1_RX.11.PeriphInc=DMA_PINC_DISABLE -Dma.I2C1_RX.11.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.I2C1_RX.11.Priority=DMA_PRIORITY_LOW -Dma.I2C1_RX.11.RequestNumber=1 -Dma.I2C1_RX.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.I2C1_RX.11.SignalID=NONE -Dma.I2C1_RX.11.SyncEnable=DISABLE -Dma.I2C1_RX.11.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.I2C1_RX.11.SyncRequestNumber=1 -Dma.I2C1_RX.11.SyncSignalID=NONE -Dma.I2C1_TX.12.Direction=DMA_MEMORY_TO_PERIPH -Dma.I2C1_TX.12.EventEnable=DISABLE -Dma.I2C1_TX.12.FIFOMode=DMA_FIFOMODE_ENABLE -Dma.I2C1_TX.12.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL -Dma.I2C1_TX.12.Instance=DMA1_Stream1 -Dma.I2C1_TX.12.MemBurst=DMA_MBURST_SINGLE -Dma.I2C1_TX.12.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.I2C1_TX.12.MemInc=DMA_MINC_ENABLE -Dma.I2C1_TX.12.Mode=DMA_NORMAL -Dma.I2C1_TX.12.PeriphBurst=DMA_PBURST_SINGLE -Dma.I2C1_TX.12.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.I2C1_TX.12.PeriphInc=DMA_PINC_DISABLE -Dma.I2C1_TX.12.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.I2C1_TX.12.Priority=DMA_PRIORITY_LOW -Dma.I2C1_TX.12.RequestNumber=1 -Dma.I2C1_TX.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.I2C1_TX.12.SignalID=NONE -Dma.I2C1_TX.12.SyncEnable=DISABLE -Dma.I2C1_TX.12.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.I2C1_TX.12.SyncRequestNumber=1 -Dma.I2C1_TX.12.SyncSignalID=NONE +Dma.ADC1.12.Direction=DMA_PERIPH_TO_MEMORY +Dma.ADC1.12.EventEnable=DISABLE +Dma.ADC1.12.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.ADC1.12.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.ADC1.12.Instance=DMA2_Stream0 +Dma.ADC1.12.MemBurst=DMA_MBURST_SINGLE +Dma.ADC1.12.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.ADC1.12.MemInc=DMA_MINC_ENABLE +Dma.ADC1.12.Mode=DMA_NORMAL +Dma.ADC1.12.PeriphBurst=DMA_PBURST_SINGLE +Dma.ADC1.12.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.ADC1.12.PeriphInc=DMA_PINC_DISABLE +Dma.ADC1.12.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.ADC1.12.Priority=DMA_PRIORITY_LOW +Dma.ADC1.12.RequestNumber=1 +Dma.ADC1.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.ADC1.12.SignalID=NONE +Dma.ADC1.12.SyncEnable=DISABLE +Dma.ADC1.12.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.ADC1.12.SyncRequestNumber=1 +Dma.ADC1.12.SyncSignalID=NONE +Dma.I2C1_RX.10.Direction=DMA_PERIPH_TO_MEMORY +Dma.I2C1_RX.10.EventEnable=DISABLE +Dma.I2C1_RX.10.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.I2C1_RX.10.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.I2C1_RX.10.Instance=DMA1_Stream0 +Dma.I2C1_RX.10.MemBurst=DMA_MBURST_SINGLE +Dma.I2C1_RX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.I2C1_RX.10.MemInc=DMA_MINC_ENABLE +Dma.I2C1_RX.10.Mode=DMA_NORMAL +Dma.I2C1_RX.10.PeriphBurst=DMA_PBURST_SINGLE +Dma.I2C1_RX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.I2C1_RX.10.PeriphInc=DMA_PINC_DISABLE +Dma.I2C1_RX.10.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.I2C1_RX.10.Priority=DMA_PRIORITY_LOW +Dma.I2C1_RX.10.RequestNumber=1 +Dma.I2C1_RX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.I2C1_RX.10.SignalID=NONE +Dma.I2C1_RX.10.SyncEnable=DISABLE +Dma.I2C1_RX.10.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.I2C1_RX.10.SyncRequestNumber=1 +Dma.I2C1_RX.10.SyncSignalID=NONE +Dma.I2C1_TX.11.Direction=DMA_MEMORY_TO_PERIPH +Dma.I2C1_TX.11.EventEnable=DISABLE +Dma.I2C1_TX.11.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.I2C1_TX.11.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.I2C1_TX.11.Instance=DMA1_Stream1 +Dma.I2C1_TX.11.MemBurst=DMA_MBURST_SINGLE +Dma.I2C1_TX.11.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.I2C1_TX.11.MemInc=DMA_MINC_ENABLE +Dma.I2C1_TX.11.Mode=DMA_NORMAL +Dma.I2C1_TX.11.PeriphBurst=DMA_PBURST_SINGLE +Dma.I2C1_TX.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.I2C1_TX.11.PeriphInc=DMA_PINC_DISABLE +Dma.I2C1_TX.11.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.I2C1_TX.11.Priority=DMA_PRIORITY_LOW +Dma.I2C1_TX.11.RequestNumber=1 +Dma.I2C1_TX.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.I2C1_TX.11.SignalID=NONE +Dma.I2C1_TX.11.SyncEnable=DISABLE +Dma.I2C1_TX.11.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.I2C1_TX.11.SyncRequestNumber=1 +Dma.I2C1_TX.11.SyncSignalID=NONE Dma.Request0=SPI1_RX Dma.Request1=SPI1_TX -Dma.Request10=USART3_TX -Dma.Request11=I2C1_RX -Dma.Request12=I2C1_TX -Dma.Request13=ADC1 -Dma.Request14=USART1_RX -Dma.Request15=USART2_RX +Dma.Request10=I2C1_RX +Dma.Request11=I2C1_TX +Dma.Request12=ADC1 +Dma.Request13=USART1_RX +Dma.Request14=TIM1_UP +Dma.Request15=TIM4_UP Dma.Request2=SPI4_RX Dma.Request3=SPI4_TX Dma.Request4=SPI3_RX @@ -353,42 +353,66 @@ Dma.SPI4_TX.3.SyncEnable=DISABLE Dma.SPI4_TX.3.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.SPI4_TX.3.SyncRequestNumber=1 Dma.SPI4_TX.3.SyncSignalID=NONE -Dma.USART1_RX.14.Direction=DMA_PERIPH_TO_MEMORY -Dma.USART1_RX.14.EventEnable=DISABLE -Dma.USART1_RX.14.FIFOMode=DMA_FIFOMODE_DISABLE -Dma.USART1_RX.14.Instance=DMA2_Stream4 -Dma.USART1_RX.14.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.USART1_RX.14.MemInc=DMA_MINC_ENABLE -Dma.USART1_RX.14.Mode=DMA_NORMAL -Dma.USART1_RX.14.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.USART1_RX.14.PeriphInc=DMA_PINC_DISABLE -Dma.USART1_RX.14.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.USART1_RX.14.Priority=DMA_PRIORITY_LOW -Dma.USART1_RX.14.RequestNumber=1 -Dma.USART1_RX.14.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.USART1_RX.14.SignalID=NONE -Dma.USART1_RX.14.SyncEnable=DISABLE -Dma.USART1_RX.14.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.USART1_RX.14.SyncRequestNumber=1 -Dma.USART1_RX.14.SyncSignalID=NONE -Dma.USART2_RX.15.Direction=DMA_PERIPH_TO_MEMORY -Dma.USART2_RX.15.EventEnable=DISABLE -Dma.USART2_RX.15.FIFOMode=DMA_FIFOMODE_DISABLE -Dma.USART2_RX.15.Instance=DMA2_Stream6 -Dma.USART2_RX.15.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.USART2_RX.15.MemInc=DMA_MINC_ENABLE -Dma.USART2_RX.15.Mode=DMA_NORMAL -Dma.USART2_RX.15.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.USART2_RX.15.PeriphInc=DMA_PINC_DISABLE -Dma.USART2_RX.15.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.USART2_RX.15.Priority=DMA_PRIORITY_LOW -Dma.USART2_RX.15.RequestNumber=1 -Dma.USART2_RX.15.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.USART2_RX.15.SignalID=NONE -Dma.USART2_RX.15.SyncEnable=DISABLE -Dma.USART2_RX.15.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.USART2_RX.15.SyncRequestNumber=1 -Dma.USART2_RX.15.SyncSignalID=NONE +Dma.TIM1_UP.14.Direction=DMA_MEMORY_TO_PERIPH +Dma.TIM1_UP.14.EventEnable=DISABLE +Dma.TIM1_UP.14.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.TIM1_UP.14.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.TIM1_UP.14.Instance=DMA2_Stream6 +Dma.TIM1_UP.14.MemBurst=DMA_MBURST_SINGLE +Dma.TIM1_UP.14.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.TIM1_UP.14.MemInc=DMA_MINC_ENABLE +Dma.TIM1_UP.14.Mode=DMA_NORMAL +Dma.TIM1_UP.14.PeriphBurst=DMA_PBURST_SINGLE +Dma.TIM1_UP.14.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.TIM1_UP.14.PeriphInc=DMA_PINC_DISABLE +Dma.TIM1_UP.14.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.TIM1_UP.14.Priority=DMA_PRIORITY_LOW +Dma.TIM1_UP.14.RequestNumber=1 +Dma.TIM1_UP.14.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.TIM1_UP.14.SignalID=NONE +Dma.TIM1_UP.14.SyncEnable=DISABLE +Dma.TIM1_UP.14.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.TIM1_UP.14.SyncRequestNumber=1 +Dma.TIM1_UP.14.SyncSignalID=NONE +Dma.TIM4_UP.15.Direction=DMA_MEMORY_TO_PERIPH +Dma.TIM4_UP.15.EventEnable=DISABLE +Dma.TIM4_UP.15.FIFOMode=DMA_FIFOMODE_ENABLE +Dma.TIM4_UP.15.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL +Dma.TIM4_UP.15.Instance=DMA2_Stream7 +Dma.TIM4_UP.15.MemBurst=DMA_MBURST_SINGLE +Dma.TIM4_UP.15.MemDataAlignment=DMA_MDATAALIGN_WORD +Dma.TIM4_UP.15.MemInc=DMA_MINC_ENABLE +Dma.TIM4_UP.15.Mode=DMA_NORMAL +Dma.TIM4_UP.15.PeriphBurst=DMA_PBURST_SINGLE +Dma.TIM4_UP.15.PeriphDataAlignment=DMA_PDATAALIGN_WORD +Dma.TIM4_UP.15.PeriphInc=DMA_PINC_DISABLE +Dma.TIM4_UP.15.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.TIM4_UP.15.Priority=DMA_PRIORITY_LOW +Dma.TIM4_UP.15.RequestNumber=1 +Dma.TIM4_UP.15.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.TIM4_UP.15.SignalID=NONE +Dma.TIM4_UP.15.SyncEnable=DISABLE +Dma.TIM4_UP.15.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.TIM4_UP.15.SyncRequestNumber=1 +Dma.TIM4_UP.15.SyncSignalID=NONE +Dma.USART1_RX.13.Direction=DMA_PERIPH_TO_MEMORY +Dma.USART1_RX.13.EventEnable=DISABLE +Dma.USART1_RX.13.FIFOMode=DMA_FIFOMODE_DISABLE +Dma.USART1_RX.13.Instance=DMA2_Stream4 +Dma.USART1_RX.13.MemDataAlignment=DMA_MDATAALIGN_BYTE +Dma.USART1_RX.13.MemInc=DMA_MINC_ENABLE +Dma.USART1_RX.13.Mode=DMA_NORMAL +Dma.USART1_RX.13.PeriphDataAlignment=DMA_PDATAALIGN_BYTE +Dma.USART1_RX.13.PeriphInc=DMA_PINC_DISABLE +Dma.USART1_RX.13.Polarity=HAL_DMAMUX_REQ_GEN_RISING +Dma.USART1_RX.13.Priority=DMA_PRIORITY_LOW +Dma.USART1_RX.13.RequestNumber=1 +Dma.USART1_RX.13.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber +Dma.USART1_RX.13.SignalID=NONE +Dma.USART1_RX.13.SyncEnable=DISABLE +Dma.USART1_RX.13.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT +Dma.USART1_RX.13.SyncRequestNumber=1 +Dma.USART1_RX.13.SyncSignalID=NONE Dma.USART2_TX.9.Direction=DMA_MEMORY_TO_PERIPH Dma.USART2_TX.9.EventEnable=DISABLE Dma.USART2_TX.9.FIFOMode=DMA_FIFOMODE_ENABLE @@ -431,27 +455,6 @@ Dma.USART3_RX.8.SyncEnable=DISABLE Dma.USART3_RX.8.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT Dma.USART3_RX.8.SyncRequestNumber=1 Dma.USART3_RX.8.SyncSignalID=NONE -Dma.USART3_TX.10.Direction=DMA_MEMORY_TO_PERIPH -Dma.USART3_TX.10.EventEnable=DISABLE -Dma.USART3_TX.10.FIFOMode=DMA_FIFOMODE_ENABLE -Dma.USART3_TX.10.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL -Dma.USART3_TX.10.Instance=DMA2_Stream7 -Dma.USART3_TX.10.MemBurst=DMA_MBURST_SINGLE -Dma.USART3_TX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE -Dma.USART3_TX.10.MemInc=DMA_MINC_ENABLE -Dma.USART3_TX.10.Mode=DMA_NORMAL -Dma.USART3_TX.10.PeriphBurst=DMA_PBURST_SINGLE -Dma.USART3_TX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE -Dma.USART3_TX.10.PeriphInc=DMA_PINC_DISABLE -Dma.USART3_TX.10.Polarity=HAL_DMAMUX_REQ_GEN_RISING -Dma.USART3_TX.10.Priority=DMA_PRIORITY_LOW -Dma.USART3_TX.10.RequestNumber=1 -Dma.USART3_TX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst,SignalID,Polarity,RequestNumber,SyncSignalID,SyncPolarity,SyncEnable,EventEnable,SyncRequestNumber -Dma.USART3_TX.10.SignalID=NONE -Dma.USART3_TX.10.SyncEnable=DISABLE -Dma.USART3_TX.10.SyncPolarity=HAL_DMAMUX_SYNC_NO_EVENT -Dma.USART3_TX.10.SyncRequestNumber=1 -Dma.USART3_TX.10.SyncSignalID=NONE FDCAN1.CalculateBaudRateNominal=200000 FDCAN1.CalculateTimeBitNominal=5000 FDCAN1.CalculateTimeQuantumNominal=1000.0 @@ -616,8 +619,8 @@ NVIC.DMA2_Stream2_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA2_Stream3_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA2_Stream4_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.DMA2_Stream5_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA2_Stream6_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true -NVIC.DMA2_Stream7_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true +NVIC.DMA2_Stream6_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true +NVIC.DMA2_Stream7_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true NVIC.DebugMonitor_IRQn=true\:0\:0\:true\:false\:true\:false\:false\:false NVIC.EXTI0_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.EXTI15_10_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true @@ -634,13 +637,13 @@ NVIC.OTG_FS_IRQn=true\:0\:0\:true\:false\:true\:true\:true\:true NVIC.PendSV_IRQn=true\:0\:0\:true\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.RCC_IRQn=true\:0\:0\:true\:false\:true\:true\:false\:true -NVIC.SDMMC1_IRQn=true\:2\:0\:true\:false\:true\:true\:true\:true +NVIC.SDMMC1_IRQn=true\:1\:0\:true\:false\:true\:true\:true\:true NVIC.SPI1_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.SPI2_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.SPI3_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.SPI4_IRQn=true\:5\:0\:true\:false\:true\:false\:true\:true NVIC.SVCall_IRQn=true\:0\:0\:true\:false\:true\:false\:false\:false -NVIC.SysTick_IRQn=true\:15\:0\:true\:false\:true\:false\:true\:false +NVIC.SysTick_IRQn=true\:0\:0\:true\:false\:true\:false\:true\:false NVIC.TIM7_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.USART1_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true NVIC.USART2_IRQn=true\:1\:0\:true\:false\:true\:true\:true\:true