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mula.da.*.(lddec|ldinc)
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@imbillow
imbillow committed Nov 23, 2024
1 parent 2180a91 commit 78bbc50
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Showing 2 changed files with 33 additions and 3 deletions.
28 changes: 25 additions & 3 deletions librz/arch/isa/xtensa/xtensa_il.c
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Original file line number Diff line number Diff line change
Expand Up @@ -725,17 +725,31 @@ static RzAnalysisLiftedILOp op_mul_aa(XtensaContext *ctx) {
MUL(VARLP("sm1"), VARLP("sm2"))))));
}

static RzAnalysisLiftedILOp op_mula_aa(XtensaContext *ctx) {
static RzAnalysisLiftedILOp f_mula__(XtensaContext *ctx, RzILOpPure *r0, RzILOpPure *r1) {
ut8 half = RRR_half(ctx);
return SEQ4(
SETG("m1", half & 0x1 ? HI16(IREG(0)) : LO16(IREG(0))),
SETG("m2", half & 0x2 ? HI16(IREG(1)) : LO16(IREG(1))),
SETG("m1", half & 0x1 ? HI16(r0) : LO16(DUP(r0))),
SETG("m2", half & 0x2 ? HI16(r1) : LO16(DUP(r1))),
SETL("acc", ACC_val()),
ACC_set(LET("sm1", SEXTRACT64(VARG("m1"), U32(0), U32(16)),
LET("sm2", SEXTRACT64(VARG("m2"), U32(0), U32(16)),
ADD(VARL("acc"), MUL(VARLP("sm1"), VARLP("sm2")))))));
}

static RzAnalysisLiftedILOp op_mula_aa(XtensaContext *ctx) {
return f_mula__(ctx, IREG(0), IREG(1));
}

static RzAnalysisLiftedILOp op_mula_da_lddec(XtensaContext *ctx) {
return SEQ2(f_mula__(ctx, IREG(2), IREG(3)),
op_lddec(ctx));
}

static RzAnalysisLiftedILOp op_mula_da_ldinc(XtensaContext *ctx) {
return SEQ2(f_mula__(ctx, IREG(2), IREG(3)),
op_ldinc(ctx));
}

// FIXME: statusflags
static RzAnalysisLiftedILOp op_mul_s(XtensaContext *ctx) {
return SEQ3(
Expand Down Expand Up @@ -905,6 +919,14 @@ static const fn_analyze_op_il fn_tbl[] = {
[XTENSA_INS_MULA_DD_LH] = op_mula_aa,
[XTENSA_INS_MULA_DD_HL] = op_mula_aa,
[XTENSA_INS_MULA_DD_HH] = op_mula_aa,
[XTENSA_INS_MULA_DA_LL_LDDEC] = op_mula_da_lddec,
[XTENSA_INS_MULA_DA_LH_LDDEC] = op_mula_da_lddec,
[XTENSA_INS_MULA_DA_HL_LDDEC] = op_mula_da_lddec,
[XTENSA_INS_MULA_DA_HH_LDDEC] = op_mula_da_lddec,
[XTENSA_INS_MULA_DA_LL_LDINC] = op_mula_da_ldinc,
[XTENSA_INS_MULA_DA_LH_LDINC] = op_mula_da_ldinc,
[XTENSA_INS_MULA_DA_HL_LDINC] = op_mula_da_ldinc,
[XTENSA_INS_MULA_DA_HH_LDINC] = op_mula_da_ldinc,
};

void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {
Expand Down
8 changes: 8 additions & 0 deletions test/db/asm/xtensa
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Original file line number Diff line number Diff line change
Expand Up @@ -159,3 +159,11 @@ d "mula.dd.ll m0, m2" 040028 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false)
d "mula.dd.hl m0, m2" 040029 0x0 (seq (set m1 (>> (var m0) (bv 32 0x10) false)) (set m2 (& (>> (var m2) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))))
d "mula.dd.lh m0, m2" 04002a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (>> (var m2) (bv 32 0x10) false)) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))))
d "mula.dd.hh m0, m2" 04002b 0x0 (seq (set m1 (>> (var m0) (bv 32 0x10) false)) (set m2 (>> (var m2) (bv 32 0x10) false)) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))))
d "mula.da.ll.lddec m0, a2, m0, a1" 140258 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (- (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr)))
d "mula.da.hl.lddec m0, a2, m0, a1" 140259 0x0 (seq (set m1 (>> (var m0) (bv 32 0x10) false)) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (- (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr)))
d "mula.da.lh.lddec m0, a2, m0, a1" 14025a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (>> (var a1) (bv 32 0x10) false)) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (- (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr)))
d "mula.da.hh.lddec m0, a2, m0, a1" 14025b 0x0 (seq (set m1 (>> (var m0) (bv 32 0x10) false)) (set m2 (>> (var a1) (bv 32 0x10) false)) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (- (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr)))
d "mula.da.ll.ldinc m0, a2, m0, a1" 140248 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (+ (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr)))
d "mula.da.hl.ldinc m0, a2, m0, a1" 140249 0x0 (seq (set m1 (>> (var m0) (bv 32 0x10) false)) (set m2 (& (>> (var a1) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (+ (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr)))
d "mula.da.lh.ldinc m0, a2, m0, a1" 14024a 0x0 (seq (set m1 (& (>> (var m0) (bv 32 0x0) false) (>> (bv 32 0xffffffff) (- (bv 32 0x20) (bv 32 0x10)) false))) (set m2 (>> (var a1) (bv 32 0x10) false)) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (+ (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr)))
d "mula.da.hh.ldinc m0, a2, m0, a1" 14024b 0x0 (seq (set m1 (>> (var m0) (bv 32 0x10) false)) (set m2 (>> (var a1) (bv 32 0x10) false)) (set acc (append (var acchi) (var acclo))) (set acc (let sm1 (>> (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m1) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (let sm2 (>> (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)) (- (bv 32 0x40) (bv 32 0x10)) (msb (cast 64 false (<< (var m2) (- (- (bv 32 0x40) (bv 32 0x10)) (bv 32 0x0)) false)))) (+ (var acc) (* (var sm1) (var sm2)))))) (set acclo (cast 32 false (& (>> (var acc) (bv 32 0x0) false) (>> (bv 64 0xffffffffffffffff) (- (bv 32 0x40) (bv 32 0x20)) false)))) (set acchi (cast 32 false (>> (var acc) (bv 32 0x20) false))) (set vAddr (+ (var a2) (bv 32 0x4))) (set m0 (loadw 0 32 (var vAddr))) (set a2 (var vAddr)))

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