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nsau
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imbillow committed Nov 24, 2024
1 parent 5813a4d commit 5c3257a
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Showing 2 changed files with 98 additions and 78 deletions.
37 changes: 28 additions & 9 deletions librz/arch/isa/xtensa/xtensa_il.c
Original file line number Diff line number Diff line change
Expand Up @@ -694,16 +694,14 @@ static RzAnalysisLiftedILOp op_movltz(XtensaContext *ctx) {
NOP());
}

#define LO2(x) EXTRACT32(x, U32(0), U32(2))
#define HI2(x) SHIFTR0(x, U32(2))
#define LO4(x) EXTRACT32(x, U32(0), U32(4))
#define HI4(x) SHIFTR0(x, U32(4))
#define HI4(x) EXTRACT32(x, U32(4), U32(4))
#define LO8(x) EXTRACT32(x, U32(0), U32(8))
#define HI8(x) SHIFTR0(x, U32(8))
#define HI8(x) EXTRACT32(x, U32(8), U32(8))
#define LO16(x) EXTRACT32(x, U32(0), U32(16))
#define HI16(x) SHIFTR0(x, U32(16))
#define HI16(x) EXTRACT32(x, U32(16), U32(16))
#define LO32(x) EXTRACT64(x, U32(0), U32(32))
#define HI32(x) SHIFTR0(x, U32(32))
#define HI32(x) EXTRACT64(x, U32(32), U32(32))

static ut8 RRR_half(XtensaContext *ctx) {
rz_warn_if_fail(FORMAT == XTENSA_INSN_FORM_RRR);
Expand Down Expand Up @@ -857,9 +855,9 @@ static RzAnalysisLiftedILOp op_nsa(XtensaContext *ctx) {
LET("b4", EQ(VARL("sign"), EXTRACT32(VARL("ars"), U32(16), U32(15))),
LET("t3", ITE(VARLP("b4"), LO16(VARL("ars")), HI16(VARL("ars"))),
LET("b3", EQ(VARL("sign"), EXTRACT32(VARLP("t3"), U32(8), U32(8))),
LET("t2", ITE(VARLP("b3"), HI8(VARLP("t3")), LO8(VARLP("t3"))),
LET("t2", ITE(VARLP("b3"), LO8(VARLP("t3")), HI8(VARLP("t3"))),
LET("b2", EQ(VARL("sign"), EXTRACT32(VARLP("t2"), U32(4), U32(4))),
LET("t1", ITE(VARLP("b2"), HI4(VARLP("t2")), LO4(VARLP("t2"))),
LET("t1", ITE(VARLP("b2"), LO4(VARLP("t2")), HI4(VARLP("t2"))),
LET("b1", EQ(VARL("sign"), EXTRACT32(VARLP("t1"), U32(2), U32(2))),
LET("b0", ITE(VARLP("b1"), EQ(EXTRACT32(VARLP("t1"), U32(0), U32(1)), VARL("sign")), EQ(EXTRACT32(VARLP("t1"), U32(3), U32(1)), VARL("sign"))),
SUB(LOGOR(
Expand All @@ -871,6 +869,27 @@ static RzAnalysisLiftedILOp op_nsa(XtensaContext *ctx) {
U32(1)))))))))))));
}

static RzAnalysisLiftedILOp op_nsau(XtensaContext *ctx) {
return SEQ3(
SETL("ars", IREG(1)),
SETL("sign", U32(0)),
SETG(REGN(0),
ITE(EQ(VARL("sign"), VARL("ars")), U32(32),
LET("b4", EQ(VARL("sign"), EXTRACT32(VARL("ars"), U32(16), U32(16))),
LET("t3", ITE(VARLP("b4"), LO16(VARL("ars")), HI16(VARL("ars"))),
LET("b3", EQ(VARL("sign"), EXTRACT32(VARLP("t3"), U32(8), U32(8))),
LET("t2", ITE(VARLP("b3"), LO8(VARLP("t3")), HI8(VARLP("t3"))),
LET("b2", EQ(VARL("sign"), EXTRACT32(VARLP("t2"), U32(4), U32(4))),
LET("t1", ITE(VARLP("b2"), LO4(VARLP("t2")), HI4(VARLP("t2"))),
LET("b1", EQ(VARL("sign"), EXTRACT32(VARLP("t1"), U32(2), U32(2))),
LET("b0", ITE(VARLP("b1"), EQ(EXTRACT32(VARLP("t1"), U32(0), U32(1)), VARL("sign")), EQ(EXTRACT32(VARLP("t1"), U32(3), U32(1)), VARL("sign"))),
LOGOR(SHIFTL0(BOOL_TO_BV(VARLP("b4"), 32), U32(4)),
LOGOR(SHIFTL0(BOOL_TO_BV(VARLP("b3"), 32), U32(3)),
LOGOR(SHIFTL0(BOOL_TO_BV(VARLP("b2"), 32), U32(2)),
LOGOR(SHIFTL0(BOOL_TO_BV(VARLP("b1"), 32), U32(1)),
BOOL_TO_BV(VARLP("b0"), 32))))))))))))))));
}

#include <rz_il/rz_il_opbuilder_end.h>

static const fn_analyze_op_il fn_tbl[] = {
Expand Down Expand Up @@ -1058,7 +1077,7 @@ static const fn_analyze_op_il fn_tbl[] = {
[XTENSA_INS_NEXP01_S] = op_nexp01_s,
[XTENSA_INS_NOP] = op_nop,
[XTENSA_INS_NSA] = op_nsa,
// [XTENSA_INS_NSAU] = op_nsau,
[XTENSA_INS_NSAU] = op_nsau,
};

void xtensa_analyze_op_rzil(XtensaContext *ctx, RzAnalysisOp *op) {
Expand Down
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