The .gitignore was being a little over enthusiastic hiding files.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>

We need both git and a working compiler to build the tools. Although
the qemu:debian9 image also has a bunch of extra dependencies it would
be fairly unusual for a user not to already have this layer available
for one of our many other docker images so lets not complicate things.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>

This image isn't going to build anything significant as it is just
intended for building test cases. In case it does end up getting
inadvertently included in a build lets aim for the minimal possible
product.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>

As this is called directly from the Makefile while determining
dependencies and it is possible the user was configured in one window
but not have credentials in the other. Let's catch the Exceptions and
deal with it quietly.

Signed-off-by: Alex Bennée <[email protected]>
Reported-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>

This allows some tests that just want to configure QEMU's source tree
to do so.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>

Not all docker images can run the check step. Let's move everything
into a common helper so we don't need to replicate checks in the
future.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>

Not all our images are able to run the tests. Rather than use features
we can just check for the existence and run-ability of gtester. If the
image has been setup for binfmt_misc it will be able to run anyway.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>

Rename DOCKER_INTERMEDIATE_IMAGES to DOCKER_PARTIAL_IMAGES and add the
incomplete cross compiler images that can build tests but can't build
QEMU itself. We also add debian, debian-bootstrap and the tricode
images to the list.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>

This test doesn't even build QEMU, it just builds and runs all the
unit tests. Intended to make checking unit tests on all docker images
easier.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>

This allows us to run a particular test on all docker images. For
example:

  make docker-test-unit

Will run the unit tests on every supported image. At the same time
rename docker-test to docker-all-tests to be clearer.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>

The addition of QEMU_TARGET was intended to ensure we fall back to
checking for the existence of an image if the build system was not
currently configured to build it. However this breaks the direct use
of the rule for building custom binfmt_misc images. We already check
for EXECUTABLE so let us just use that as a proxy for deciding if we
are just going to check the image exits.

Signed-off-by: Alex Bennée <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>

When a check fails we currently just report why we failed. This is not
totally helpful to people who want to boot-strap a new image. Report a
hint as to why it failed.

Signed-off-by: Alex Bennée <[email protected]>
Suggested-by: Fam Zheng <[email protected]>

…to Salsa

This silents the following warning:

  Cloning into './debootstrap.git'...
  warning: redirecting to https://salsa.debian.org/installer-team/debootstrap.git/

See https://lists.debian.org/debian-devel-announce/2018/01/msg00004.html

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>

This is just a note that later versions of debootstrap don't
technically need this hack.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>

We do a minimum version check for the debootstrap but if the distro
has added their own minor version tick it would fail and fall-back to
the SCM version. This is sub-optimal as the latest/greatest version
may be broken at any one particular time. We fix that with a little
sed magic on the version string before passing to our ugly shell
versioning check.

Signed-off-by: Alex Bennée <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>

Setting up binfmt_misc is outside of the scope of the docker.py script
but we can at least validate it with any given executable so we have a
more useful error message than the sed line of deboostrap failing
cryptically.

Signed-off-by: Alex Bennée <[email protected]>
Reported-by: Richard Henderson <[email protected]>

The combination of being rather esoteric and needing to support mmap @
0 means this only ever worked under translation. It has now regressed
even further and is no longer useful. Kill it.

Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>

…nd cdrom

In ed6e216 ("linux-aio: properly bubble up errors from initialzation"),
I only added a bdrv_attach_aio_context callback for the bdrv_file
driver. There are several other drivers that use the shared
aio_plug callback, though, and they will trip the assertion added to
aio_get_linux_aio because they did not call aio_setup_linux_aio first.
Add the appropriate callback definition to the affected driver
definitions.

Fixes: ed6e216 ("linux-aio: properly bubble up errors from initialization")
Reported-by: Farhan Ali <[email protected]>
Signed-off-by: Nishanth Aravamudan <[email protected]>
Reviewed-by: John Snow <[email protected]>
Message-id: [email protected]
Cc: Eric Blake <[email protected]>
Cc: Kevin Wolf <[email protected]>
Cc: John Snow <[email protected]>
Cc: Max Reitz <[email protected]>
Cc: Stefan Hajnoczi <[email protected]>
Cc: Fam Zheng <[email protected]>
Cc: Paolo Bonzini <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Stefan Hajnoczi <[email protected]>

Calling qcrypto_init ensures that all relevant initialization is
done. In particular this honours the debugging settings and thread
settings.

Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Daniel P. Berrangé <[email protected]>

The test-vmstate test is a bit chatty because it triggers various
expected failure scenarios and the code in question uses error_report
instead of accepting 'Error **errp' parameters. To silence this test the
stubs for error_vprintf() were changed to send errors via
g_test_message() instead of stderr:

  commit 28017e0
  Author: Paolo Bonzini <[email protected]>
  Date:   Mon Oct 24 18:31:03 2016 +0200

    tests: send error_report to test log

    Implement error_vprintf to send the output of error_report to
    the test log.  This silences test-vmstate.

    Signed-off-by: Paolo Bonzini <[email protected]>
    Message-Id: <[email protected]>

Unfortunately this change has global impact across the entire test suite
and means that when tests fail for unexpected reasons, the message is
not displayed on stderr. eg when using &error_abort in a call the test
merely prints

  Unexpected error in qcrypto_tls_session_check_certificate() at crypto/tlssession.c:280:

and the actual error message is hidden, making it impossible to diagnose
the failure. This is especially problematic in CI or build systems where
it isn't possible to easily pass the --debug-log flag to tests and
re-run with the test log visible.

This change makes the previous big hammer much more nuanced, providing a
flag in the stub error_vprintf() that can used on a per-test basis to
silence the errors. Only the test-vmstate silences errors initially.

Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Daniel P. Berrangé <[email protected]>

Most of the TLS related tests are passing an in a "Error" object to
methods that are expected to fail, but then ignoring any error that is
set and instead asserting on a return value. This means that when an
error is unexpectedly raised, no information about it is printed out,
making failures hard to diagnose. Changing these tests to pass in
&error_abort will make unexpected failures print messages to stderr.

Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Daniel P. Berrangé <[email protected]>

When gnutls negotiates TLS 1.3 instead of 1.2, the order of messages
sent by the handshake changes. This exposed a logic bug in the test
suite which caused us to wait for the server to see handshake
completion, but not wait for the client to see completion. The result
was the client didn't receive the certificate for verification and the
test failed.

This is exposed in Fedora 29 rawhide which has just enabled TLS 1.3 in
its GNUTLS builds.

Reviewed-by: Eric Blake <[email protected]>
Signed-off-by: Daniel P. Berrangé <[email protected]>

I would guess it won't happen normally, but this should ease Coverity.

>>>     CID 1394385:  Integer handling issues  (OVERFLOW_BEFORE_WIDEN)
>>>     Potentially overflowing expression "pages->used * 8192U" with type "unsigned int" (32 bits, unsigned) is evaluated using 32-bit arithmetic, and then used in a context that expects an expression of type "uint64_t" (64 bits, unsigned).
854         transferred = pages->used * TARGET_PAGE_SIZE + p->packet_len;

Fixes: CID 1394385
CC: Juan Quintela <[email protected]>
Signed-off-by: Peter Xu <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Juan Quintela <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

We've been getting the warning:

migration_iteration_finish: Unknown ending state 2

on a cancel.

I think that's originally due to 39b9e17;  although
I've only seen the warning, I think that in some cases
that we could find the VM stays paused after a cancel where
it should restart.

Signed-off-by: Dr. David Alan Gilbert <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Reviewed-by: Juan Quintela <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

Fix outgoing migration which was crashing in
vmstate_hda_audio_stream_buf_needed, I think the problem
is that we have room for upto 4 streams in the array but only
use 2, when we come to try and save the state of the unused
streams we hit st->state == NULL.

Fixes: 280c1e1
Signed-off-by: Dr. David Alan Gilbert <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Juan Quintela <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

We shouldn't update the received bitmap if we're the source VM.  This
fixes a breakage when release-ram is enabled on postcopy.

Signed-off-by: Peter Xu <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Juan Quintela <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

Postcopy recovery won't work well with release-ram capability since
release-ram will drop the page buffer as long as the page is put into
the send buffer.  So if there is a network failure happened, any page
buffers that have not yet reached the destination VM but have already
been sent from the source VM will be lost forever.  Let's refuse the
client from resuming such a postcopy migration.  Luckily release-ram was
designed to only be used when src and destination VMs are on the same
host, so it should be fine.

Signed-off-by: Peter Xu <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Juan Quintela <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

The only possible change of last_byte is when it reaches the edge.
Setting it every time might let last_byte contain an invalid data when
memory corruption is detected, then the check of the next byte will be
incorrect.  For example, a single page corruption at address 0x14ad000
will also lead to a "fake" corruption at 0x14ae000:

  Memory content inconsistency at 14ad000 first_byte = 44 last_byte = 44 current = ef hit_edge = 0
  Memory content inconsistency at 14ae000 first_byte = 44 last_byte = ef current = 44 hit_edge = 0

After the patch, it'll only report the corrputed page:

  Memory content inconsistency at 14ad000 first_byte = 44 last_byte = 44 current = ef hit_edge = 0

Signed-off-by: Peter Xu <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Juan Quintela <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

…anup_bh

migrate_fd_connect duplicate initialize expected_downtime and cleanup_bh.

Signed-off-by: Lidong Chen <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Juan Quintela <[email protected]>
Signed-off-by: Dr. David Alan Gilbert <[email protected]>

Signed-off-by: Peter Maydell <[email protected]>

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Palmer Dabbelt <[email protected]>

- Inline PTE_TABLE check for better readability
- Change access checks from ternary operator to if
- Improve readibility of User page U mode and SUM test
- Disallow non U mode from fetching from User pages
- Add reserved PTE flag check: W or W|X
- Add misaligned PPN check
- Set READ protection for PTE X flag and mstatus.mxr
- Use memory_region_is_ram in pte update

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>

The PLIC previously used a mutex to protect against concurrent
access to the claimed and pending bitfields. Instead of using
a mutex, we update the bitfields using atomic_cmpxchg.

Rename sifive_plic_num_irqs_pending to sifive_plic_irqs_pending
and add an early out if any interrupts are pending as the
count of pending interrupts is not used.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>

This commit is intended to improve readability.
There is no change to the logic.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>

Change the API of riscv_set_local_interrupt to take a
write mask and value to allow setting and clearing of
multiple local interrupts atomically in a single call.
Rename the new function to riscv_cpu_update_mip.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

This patch makes op_helper.c contain only instruction
operation helpers used by translate.c and moves any
unrelated cpu helpers into cpu_helper.c. No logic is
changed by this patch.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>

* Add user-mode CSR defininitions.
* Reorder CSR definitions to match the specification.
* Change H mode interrupt comment to 'reserved'.
* Remove unused X_COP interrupt.
* Add user-mode interrupts.
* Remove erroneous until comments on machine mode interrupts.
* Move together paging mode and page table bit definitions.
* Move together interrupt and exception cause definitions.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>

Previous CSR code uses csr_read_helper and csr_write_helper
to update CSR registers however this interface prevents
atomic read/modify/write CSR operations; in addition
there is no trap-free method to access to CSRs due
to the monolithic CSR functions call longjmp.

The current iCSR interface is not safe to be called by
target/riscv/gdbstub.c as privilege checks or missing CSRs
may call longjmp to generate exceptions. It needs to
indicate existence so traps can be generated in the
CSR instruction helpers.

This commit moves CSR access from the monolithic switch
statements in target/riscv/op_helper.c into modular
read/write functions in target/riscv/csr.c using a new
function pointer table for dispatch (which can later
be used to allow CPUs to hook up model specific CSRs).

A read/modify/write interface is added to support atomic
CSR operations and a non-trapping interface is added
to allow exception-free access to CSRs by the debugger.

The CSR functions and CSR dispatch table are ordered
to match The RISC-V Instruction Set Manual, Volume II:
Privileged Architecture Version 1.10, 2.2 CSR Listing.

An API is added to allow derived cpu instances to modify
or implement new CSR operations.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

CSR predicate functions are added to the CSR table.
mstatus.FS and counter enable checks are moved
to predicate functions and two new predicates are
added to check misa.S for s* CSRs and a new PMP
CPU feature for pmp* CSRs.

Processors that don't implement S-mode will trap
on access to s* CSRs and processors that don't
implement PMP will trap on accesses to pmp* CSRs.

PMP checks are disabled in riscv_cpu_handle_mmu_fault
when the PMP CPU feature is not present.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Cc: Richard Henderson <[email protected]>
Signed-off-by: Michael Clark <[email protected]>
Reviewed-by: Michael Clark <[email protected]>

Modifed from Richard Henderson's patch [1] to integrate
with the new control and status register implementation.

[1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html

Note: the f* CSRs already mark mstatus.FS dirty using
env->mstatus |= mstatus.FS so the bug in the first
spin of this patch has been fixed in a prior commit.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Cc: Richard Henderson <[email protected]>
Signed-off-by: Michael Clark <[email protected]>
Reviewed-by: Michael Clark <[email protected]>

Co-authored-by: Richard Henderson <[email protected]>
Co-authored-by: Michael Clark <[email protected]>

This adds the necessary minimum to support S-mode
virtualization for priv ISA >= v1.10

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Cc: Matthew Suozzo <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Co-authored-by: Matthew Suozzo <[email protected]>
Co-authored-by: Michael Clark <[email protected]>

Add carriage return that was erroneously removed
when converting to qemu_log. Change hard coded
core number to the actual hartid.

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

* Add riscv prefix to raise_exception function
* Add riscv prefix to CSR read/write functions
* Add riscv prefix to signal handler function
* Add riscv prefix to get fflags function
* Remove redundant declaration of riscv_cpu_init
  and rename cpu_riscv_init to riscv_cpu_init
* rename riscv_set_mode to riscv_cpu_set_mode

Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

The mode variable only uses the lower 4-bits (M,H,S,U) so
replace the GCC specific __builtin_popcount with ctpop8.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

We can't allow the supervisor to control SEIP as this would allow the
supervisor to clear a pending external interrupt which will result in
lost a interrupt in the case a PLIC is attached. The SEIP bit must be
hardware controlled when a PLIC is attached.

This logic was previously hard-coded so SEIP was always masked even
if no PLIC was attached. This patch adds riscv_cpu_claim_interrupts
so that the PLIC can register control of SEIP. In the case of models
without a PLIC (spike), the SEIP bit remains software controlled.

This interface allows for hardware control of supervisor timer and
software interrupts by other interrupt controller models.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

gen methods should access state from DisasContext. Add misa
field to the DisasContext struct and remove CPURISCVState
argument from all gen methods.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Cc: Emilio G. Cota <[email protected]>
Signed-off-by: Michael Clark <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>

Add misa checks for M, A, F and D extensions and if they are
not present generate illegal instructions. This improves
emulation accurary for harts with a limited set of extensions.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Cc: Emilio G. Cota <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

This patch adds support for writing misa. misa is validated based
on rules in the ISA specification. 'E' is mutually exclusive with
all other extensions. 'D' depends on 'F' so 'D' bit is dropped
if 'F' is not present. A conservative approach to consistency is
taken by flushing the translation cache on misa writes. misa_mask
is added to the CPU struct to store the original set of extensions.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

A missing shift made updates to the low order bits
of timecmp erroneously copy the old low order bits
into the high order bits of the 64-bit timecmp
register. Add the missing shift and rename timecmp
local variables to timecmp_hi and timecmp_lo.

This bug didn't show up as the low order bits are
usually written first followed by the high order
bits meaning the high order bits contained an invalid
value between the timecmp_lo and timecmp_hi update.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Co-Authored-by: Johannes Haring <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

The address calculation for the pending bitfield had
a copy paste bug. This bug went unnoticed because the Linux
PLIC driver does not read the pending bitfield, rather it
reads pending interrupt numbers from the claim register
and writes acknowledgements back to the claim register.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Reported-by: Vincent Siles <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Previously the second UARTs on the sifive_e and sifive_u machines
where disabled due to check-qtest-riscv32 and check-qtest-riscv64
failures. Recent changes in the QEMU core serial code have
resolved these failures so the second UARTs can be instantiated.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Remove machine generated constraints that are not
referenced by the pseudo-instruction constraints.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Refer to the RISC-V PSABI specification for details:

- https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md

Cc: Michael Tokarev <[email protected]>
Cc: Richard Henderson <[email protected]>
Cc: Alistair Francis <[email protected]>
Reviewed-by: Laurent Vivier <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

This change checks elf_flags for EF_RISCV_RVE and if
present uses the RVE linux syscall ABI which uses t0
for the syscall number instead of a7.

Warn and exit if a non-RVE ABI binary is run on a
cpu with the RVE extension as it is incompatible.

Cc: Palmer Dabbelt <[email protected]>
Cc: Sagar Karandikar <[email protected]>
Cc: Bastian Koppelmann <[email protected]>
Cc: Alistair Francis <[email protected]>
Co-authored-by: Kito Cheng <[email protected]>
Co-authored-by: Michael Clark <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Support for separate firmware and kernel payload is added
by updating BBL to read optional preloaded kernel address
attributes from device-tree using a similar mechanism to
that used to pass init ramdisk addresses to linux kernel.

    chosen {
        riscv,kernel-start = <0x00000000 0x80200000>;
        riscv,kernel-end = <0x00000000 0x80590634>;
    };

These attributes are added by QEMU and read by BBL when combining
-bios <firmware-image> and -kernel <kernel-image> options. e.g.

$ qemu-system-riscv64 -machine virt -bios bbl -kernel vmlinux

With this change, bbl can be compiled without --with-payload
and the dummy payload alignment is altered to make the memory
footprint of the firmware-only bbl smaller. The dummy payload
message is updated to indicate the alternative load method.

This load method could also be supported by a first stage boot
loader that reads seperate firmware and kernel from SPI flash.
The main advantage of this new mechanism is that it eases kernel
development by avoiding the riscv-pk packaging step after kernel
builds, makes building per repository artefacts for CI simpler,
and mimics bootloaders on other platforms that can load a kernel
image file directly. Ultimately BBL should use an SPI driver to
load the kernel image however this mechanism supports use cases
such such as QEMU's -bios, -kernel and -initrd options following
examples from other platforms that pass kernel entry to firmware
via device-tree.

The board is also changed to use the firmware address from the
loaded firmware or combined firmware+kernel. This is normally
equal to the DRAM base address of 0x8000_0000, however now it
is possible to boot firmware at different load addresses because
the reset code jumps to the actual firmware entry address.

Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

This effectively changes riscv_cpu_update_mip
from edge to level. i.e. cpu_interrupt or
cpu_reset_interrupt are called regardless of
the current interrupt level.

Fixes WFI doesn't return when a IPI is issued:

- riscvarchive#132

To test:

1) Apply RISC-V Linux CPU hotplug patch:

- http://lists.infradead.org/pipermail/linux-riscv/2018-May/000603.html

2) Enable CONFIG_CPU_HOTPLUG in linux .config

3) Try to offline and online cpus:

  echo 1 > /sys/devices/system/cpu/cpu2/online
  echo 0 > /sys/devices/system/cpu/cpu2/online
  echo 1 > /sys/devices/system/cpu/cpu2/online

Reported-by: Atish Patra <[email protected]>
Cc: Atish Patra <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Add the SiFive Test device to 'sifive_e' and 'sifive_u'
machines so that test cases can shutdown QEMU and signal
an exit code. The SiFive Test Finisher is a real device
that exists in the RTL to allow exiting simulations.

Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

If vectored interrupts are enabled (bits[1:0]
of mtvec/stvec == 1) then use the following
logic for trap entry address calculation:

 pc = mtvec + cause * 4

In addition to adding support for vectored interrupts
this patch simplifies the interrupt delivery logic
by making sync/async cause decoding and encoding
steps distinct.

The cause code and the sign bit indicating sync/async
is split at the beginning of the function and fixed
cause is renamed to cause. The MSB setting for async
traps is delayed until setting mcause/scause to allow
redundant variables to be eliminated. Some variables
are renamed for conciseness and moved so that decls
are at the start of the block.

Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Cc: Palmer Dabbelt <[email protected]>
Cc: Alistair Francis <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Writes to the SiFive PRCI registers are preserved while leaving the
ready bits set for the HFX/HFR oscillators and the lock bit set for the
PLL.

Signed-off-by: Nathaniel Graff <[email protected]>
Reviewed-by: Michael Clark <[email protected]>

The watermark bits are set in the interrupt pending register according
to the configuration of txcnt and rxcnt in the txctrl and rxctrl
registers.

Since the UART TX does not implement a FIFO, the txwm bit is set as long
as the TX watermark level is greater than zero.

Signed-off-by: Nathaniel Graff <[email protected]>
Reviewed-by: Michael Clark <[email protected]>

According to the RISC-V priv. v1.10 ISA document,
pmpaddr register stores (base_addr | (size/2 - 1)) >> 2 for a
NAPOT-encoded address.
However, the current code decodes (base_addr | (size - 1)) >> 3 which
leads to a wrong base address and size.

Signed-off-by: Dayeol Lee <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Michael Clark <[email protected]>

A wrong address is passed to `pmp_is_in_range` while checking if a
memory access is within a PMP range.
Since the ending address of the pmp range (i.e., pmp_state.addr[i].ea)
is set to the last address in the range (i.e., pmp base + pmp size - 1),
memory accesses containg the last address in the range will always fail.

For example, assume that a PMP range is 4KB from 0x87654000 such that
the last address within the range is 0x87654fff.
1-byte access to 0x87654fff should be considered to be fully inside the
PMP range.
However the access now fails and complains partial inclusion because
pmp_is_in_range(env, i, addr + size) returns 0 whereas
pmp_is_in_range(env, i, addr) returns 1.

Signed-off-by: Dayeol Lee <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Michael Clark <[email protected]>

cpu_init() was removed since 2.12, so drop the define that is now unused.

Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Michael Clark <[email protected]>

An SOC child object was added in a previous commit which
created a static toplogy of the SOC and apparently external
periphery, however, the intention is to make the peripheral
configuration of the 'sifive_e' and 'sifive_u' machines
dynamic so any static structs need to be removed. The first
step towards creating dynamic topology is to remove the
static topology, which in effect, created a wrapper around
riscv_hart_array.

Signed-off-by: Michael Clark <[email protected]>

Renamed RISCV_FEATURE_MISA_RW to RISCV_FEATURE_MISA

Signed-off-by: Michael Clark <[email protected]>

- Due to the design of the disassembler, the immediate is not
  known during decoding of the opcode; so to handle compressed
  encodings with reserved immediate values (non-zero), we need
  to add an additional check during decompression to match
  reserved encodings with zero immediates and translate them
  into the illegal instruction.

The following compressed opcodes have reserved encodings with
zero immediates: c.addi4spn, c.addi, c.lui, c.addi16sp, c.srli,
c.srai, c.andi and c.slli

Signed-off-by: Michael Clark <[email protected]>

Signed-off-by: Michael Clark <[email protected]>

The constraint for `rdinstreth` was comparing the csr number to 0xc80,
which is `cycleh` instead. Fix this.

Author: Wladimir J. van der Laan <[email protected]>
Signed-off-by: Michael Clark <[email protected]>

Attach up to 16 serial devices, densely packed in the memory map and
registered in the FDT.  To ensure that BBL continues to find the default
one, we register it last so that it ends up at the top of the fdt.

Signed-off-by: Nathaniel Wesley Filardo <[email protected]>