Skip to content
This repository has been archived by the owner on Apr 13, 2019. It is now read-only.

Commit

Permalink
Merge branch 'qemu-for-testing' into riscv-all
Browse files Browse the repository at this point in the history
  • Loading branch information
Michael Clark committed Oct 2, 2018
2 parents f97df93 + 1f32abd commit 3ee161b
Show file tree
Hide file tree
Showing 22 changed files with 1,656 additions and 107 deletions.
1 change: 1 addition & 0 deletions Makefile.objs
Original file line number Diff line number Diff line change
Expand Up @@ -228,6 +228,7 @@ trace-events-subdirs += hw/nvram
trace-events-subdirs += hw/pci
trace-events-subdirs += hw/pci-host
trace-events-subdirs += hw/ppc
trace-events-subdirs += hw/riscv
trace-events-subdirs += hw/rdma
trace-events-subdirs += hw/rdma/vmw
trace-events-subdirs += hw/s390x
Expand Down
2 changes: 2 additions & 0 deletions configure
Original file line number Diff line number Diff line change
Expand Up @@ -7044,12 +7044,14 @@ case "$target_name" in
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml"
target_compiler=$cross_cc_riscv32
;;
riscv64)
TARGET_BASE_ARCH=riscv
TARGET_ABI_DIR=riscv
mttcg=yes
gdb_xml_files="riscv-cpu.xml riscv-fpu.xml riscv-csr.xml"
target_compiler=$cross_cc_riscv64
;;
sh4|sh4eb)
Expand Down
43 changes: 43 additions & 0 deletions gdb-xml/riscv-cpu.xml
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.cpu">
<reg name="x0" bitsize="64"/>
<reg name="x1" bitsize="64"/>
<reg name="x2" bitsize="64"/>
<reg name="x3" bitsize="64"/>
<reg name="x4" bitsize="64"/>
<reg name="x5" bitsize="64"/>
<reg name="x6" bitsize="64"/>
<reg name="x7" bitsize="64"/>
<reg name="x8" bitsize="64"/>
<reg name="x9" bitsize="64"/>
<reg name="x10" bitsize="64"/>
<reg name="x11" bitsize="64"/>
<reg name="x12" bitsize="64"/>
<reg name="x13" bitsize="64"/>
<reg name="x14" bitsize="64"/>
<reg name="x15" bitsize="64"/>
<reg name="x16" bitsize="64"/>
<reg name="x17" bitsize="64"/>
<reg name="x18" bitsize="64"/>
<reg name="x19" bitsize="64"/>
<reg name="x20" bitsize="64"/>
<reg name="x21" bitsize="64"/>
<reg name="x22" bitsize="64"/>
<reg name="x23" bitsize="64"/>
<reg name="x24" bitsize="64"/>
<reg name="x25" bitsize="64"/>
<reg name="x26" bitsize="64"/>
<reg name="x27" bitsize="64"/>
<reg name="x28" bitsize="64"/>
<reg name="x29" bitsize="64"/>
<reg name="x30" bitsize="64"/>
<reg name="x31" bitsize="64"/>
<reg name="pc" bitsize="64"/>
</feature>
11 changes: 11 additions & 0 deletions gdb-xml/riscv-csr.xml
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.csr">
<reg name="misa" bitsize="64" regnum="0x342"/>
</feature>
43 changes: 43 additions & 0 deletions gdb-xml/riscv-fpu.xml
Original file line number Diff line number Diff line change
@@ -0,0 +1,43 @@
<?xml version="1.0"?>
<!-- Copyright (C) 2018 Free Software Foundation, Inc.
Copying and distribution of this file, with or without modification,
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->

<!DOCTYPE feature SYSTEM "gdb-target.dtd">
<feature name="org.gnu.gdb.riscv.fpu">
<reg name="f0" bitsize="64"/>
<reg name="f1" bitsize="64"/>
<reg name="f2" bitsize="64"/>
<reg name="f3" bitsize="64"/>
<reg name="f4" bitsize="64"/>
<reg name="f5" bitsize="64"/>
<reg name="f6" bitsize="64"/>
<reg name="f7" bitsize="64"/>
<reg name="f8" bitsize="64"/>
<reg name="f9" bitsize="64"/>
<reg name="f10" bitsize="64"/>
<reg name="f11" bitsize="64"/>
<reg name="f12" bitsize="64"/>
<reg name="f13" bitsize="64"/>
<reg name="f14" bitsize="64"/>
<reg name="f15" bitsize="64"/>
<reg name="f16" bitsize="64"/>
<reg name="f17" bitsize="64"/>
<reg name="f18" bitsize="64"/>
<reg name="f19" bitsize="64"/>
<reg name="f20" bitsize="64"/>
<reg name="f21" bitsize="64"/>
<reg name="f22" bitsize="64"/>
<reg name="f23" bitsize="64"/>
<reg name="f24" bitsize="64"/>
<reg name="f25" bitsize="64"/>
<reg name="f26" bitsize="64"/>
<reg name="f27" bitsize="64"/>
<reg name="f28" bitsize="64"/>
<reg name="f29" bitsize="64"/>
<reg name="f30" bitsize="64"/>
<reg name="f31" bitsize="64"/>
<reg name="f32" bitsize="64"/>
</feature>
1 change: 1 addition & 0 deletions hw/riscv/Makefile.objs
Original file line number Diff line number Diff line change
Expand Up @@ -2,6 +2,7 @@ obj-y += boot.o
obj-y += riscv_htif.o
obj-y += riscv_hart.o
obj-y += sifive_e.o
obj-y += sifive_clic.o
obj-y += sifive_clint.o
obj-y += sifive_prci.o
obj-y += sifive_plic.o
Expand Down
Loading

0 comments on commit 3ee161b

Please sign in to comment.