The srmcfg
register is an SXLEN-bit read/write register used to configure a
Resource Control ID (RCID
) and a Monitoring Counter ID (MCID
). Both RCID
and MCID
are WARL fields. The register is formatted as shown in Supervisor Resource Management Configuration (srmcfg
) register for SXLEN=64
when SXLEN=64 and Supervisor Resource Management Configuration (srmcfg
) register for SXLEN=32 when SXLEN=32. The CSR number is 0x181.
The RCID
and MCID
accompany each request made by the hart to shared resource
controllers. The RCID
is used to determine the resource allocations
(e.g., cache occupancy limits, memory bandwidth limits, etc.) to enforce. The
MCID
is used to identify a counter to monitor resource usage.
srmcfg
) register for SXLEN=64{reg: [ {bits: 12, name: 'RCID'}, {bits: 4, name: 'WPRI'}, {bits: 12, name: 'MCID'}, {bits: 36, name: 'WPRI'}, ], config:{lanes: 2, hspace:1024}}
srmcfg
) register for SXLEN=32{reg: [ {bits: 12, name: 'RCID'}, {bits: 4, name: 'WPRI'}, {bits: 12, name: 'MCID'}, {bits: 4, name: 'WPRI'}, ], config:{lanes: 1, hspace:1024}}
The RCID
and MCID
configured in the srmcfg
CSR apply to all privilege
modes cite:[PRIV] of software execution on that hart by default, but this
behavior may be overridden by future extensions.
If extension Smstateen is implemented together with Ssqosid, then Ssqosid also
requires the bit 55 in mstateen0
introduced by Priv 1.14 to be implemented. If
bit 55 of mstateen0
is 0, attempts to access srmcfg
in privilege modes less
privileged than M-mode raise an illegal-instruction exception. If bit 55 of
mstateen0
is 1 or if extension Smstateen is not implemented, attempts to
access srmcfg
when V=1
raise a virtual-instruction exception.
Note
|
A reset value of 0 is suggested for the Typically, fewer bits are allocated for The |
Note
|
In VM environments, hypervisors usually manage resource allocations, keeping
the Guest OS out of QoS flows. If needed, the hypervisor can virtualize
During context switches, the supervisor may choose to execute with the |