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Server Platform Test Specification

Server Platform Hardware Requirements

RISC-V Harts

ID# Algorithm

ME_RVA_010_010

For each application processor hart:

  1. Determine the ISA node in ACPI RHCT table for that hart.

  2. Parse the ISA string in the ISA node and verify that all mandatory extensions are supported.

  3. Verify that the ISA string matches that of hart 0.

  4. Report the ISA string of hart 0 into the test output log.

ME_RVA_020_010

See T_RVA_010_010.

ME_RVA_030_010

  1. The T_RVA_010_010 verifies that all ISA strings are identical.

  2. For each ISA extension reported in the ISA string, if there are CSRs associated with that extension, then probe the CSR to determine the width of the CSR fields and the legal encodings on each application processor hart. The CSR field widths and legal encodings supported by each hart must match that of hart 0.

ME_RVA_040_010

See ME_RVA_030_010.

ME_RVA_050_010

No test.

MF_RVA_060_010

Install 4 instruction address match triggers using the debug triggers SBI and verify that each trigger fires.

MF_RVA_060_020

Install 4 load address match triggers using the debug triggers SBI and verify that each trigger fires.

MF_RVA_060_030

Install 4 store address match triggers using the debug triggers SBI and verify that each trigger fires.

MF_RVA_060_040

Install an icount trigger using the debug triggers SBI and verify single-step.

MF_RVA_060_050

  1. Install an interrupt trigger to match supervisor timer interrupt using the debug triggers SBI.

  2. Program a timer deadline in stimecmp

  3. Verify that the trigger fires on reaching the programmed deadline.

MF_RVA_060_060

  1. Install an exception trigger to match ECALL to S-mode exception using the debug triggers SBI.

  2. Transition to U-mode and invoke an ECALL.

  3. Verify that the trigger fires.

MF_RVA_060_070

  1. Verify hcontext exists.

  2. Repeat MF_RVA_060_010 and MF_RVA_060_050 with a matching and non-matching hcontext value.

ME_RVA_060_080

  1. Install and read-back triggers with VMID values between 0 and VMIDLEN.

MF_RVA_060_090

  1. Verify scontext exists.

  2. Repeat MF_RVA_060_010 and MF_RVA_060_050 with a matching and non-matching scontext value.

ME_RVA_060_100

  1. Install and read-back triggers with ASID values between 0 and ASIDLEN.

ME_RVA_070_010

  1. Request delegation of all HPM counters using the SBI.

  2. Verify at least 6 programmable HPM counter are implemented.

  3. Verify that the scountovf CSR is implemented

  4. Verify cycles and instret are writeable.

  5. Verify ability to toggle counter enable for each implemented HPM, cycles, and instret counters.

RISC-V SoC

ID# Algorithm

ME_HSOC_010_010

The Server SoC tests must pass cite:[ServerSoCTest].

ME_HSOC_020_010

FIXME.

Peripherals

ID# Algorithm

ME_HPER_010_010

FIXME.

MF_HPER_020_010

FIXME.

MF_HPER_030_010

FIXME XHCI test validating register values.

MF_HPER_040_010

FIXME XHCI test validating register values.

MF_HPER_050_010

FIXME AHCI test validating register values.

MF_HPER_060_010

FIXME AHCI test validating register values.

MF_HPER_070_010

FIXME UEFI RT based test.

MF_HPER_080_010

FIXME.

MF_HPER_090_010

FIXME.

Server Platform Firmware Requirements

ID# Algorithm

ME_FIRM_010_010

The BRS-I tests must pass cite:[BRSTest].

ME_FIRM_020_010

FIXME.

ME_FIRM_030_010

FIXME.

ME_FIRM_040_010

FIXME.

ME_FIRM_050_010

FIXME.

ME_FIRM_060_010

FIXME.

ME_FIRM_070_010

FIXME.

ME_FIRM_080_010

FIXME.

ME_FIRM_090_010

FIXME.

ME_FIRM_100_010

FIXME.

ME_FIRM_110_010

FIXME.

Server Platform Security Requirements

ID# Algorithm

ME_SEC_010_010

FIXME

ME_SEC_011_010

FIXME

ME_SEC_012_010

FIXME

ME_SEC_020_010

FIXME

ME_SEC_030_010

FIXME

ME_SEC_040_010

FIXME

ME_SEC_050_010

FIXME

ME_SEC_060_010

FIXME