From 4e61c25bdd4ec4e7b9894a6c85a997b496a83bb2 Mon Sep 17 00:00:00 2001 From: David Harris Date: Wed, 15 Nov 2023 07:46:02 -0800 Subject: [PATCH 1/2] Added *RV64 to checkISA for RV64 M tests that lost this attribute. --- riscv-test-suite/rv64i_m/M/src/divu-01.S | 2 +- riscv-test-suite/rv64i_m/M/src/mul-01.S | 2 +- riscv-test-suite/rv64i_m/M/src/mulh-01.S | 2 +- riscv-test-suite/rv64i_m/M/src/mulhsu-01.S | 2 +- riscv-test-suite/rv64i_m/M/src/mulhu-01.S | 2 +- riscv-test-suite/rv64i_m/M/src/rem-01.S | 2 +- riscv-test-suite/rv64i_m/M/src/remu-01.S | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/riscv-test-suite/rv64i_m/M/src/divu-01.S b/riscv-test-suite/rv64i_m/M/src/divu-01.S index b2b44d740..b51194982 100644 --- a/riscv-test-suite/rv64i_m/M/src/divu-01.S +++ b/riscv-test-suite/rv64i_m/M/src/divu-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",divu) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",divu) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/M/src/mul-01.S b/riscv-test-suite/rv64i_m/M/src/mul-01.S index 63513d9c2..331961d90 100644 --- a/riscv-test-suite/rv64i_m/M/src/mul-01.S +++ b/riscv-test-suite/rv64i_m/M/src/mul-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mul) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",mul) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/M/src/mulh-01.S b/riscv-test-suite/rv64i_m/M/src/mulh-01.S index 95db04788..bb5878d07 100644 --- a/riscv-test-suite/rv64i_m/M/src/mulh-01.S +++ b/riscv-test-suite/rv64i_m/M/src/mulh-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulh) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",mulh) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S b/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S index bb239b8e9..10aa76d26 100644 --- a/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S +++ b/riscv-test-suite/rv64i_m/M/src/mulhsu-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulhsu) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",mulhsu) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/M/src/mulhu-01.S b/riscv-test-suite/rv64i_m/M/src/mulhu-01.S index 25558c13e..70ac34978 100644 --- a/riscv-test-suite/rv64i_m/M/src/mulhu-01.S +++ b/riscv-test-suite/rv64i_m/M/src/mulhu-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",mulhu) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",mulhu) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/M/src/rem-01.S b/riscv-test-suite/rv64i_m/M/src/rem-01.S index 07d4fa1ce..f1e8d066e 100644 --- a/riscv-test-suite/rv64i_m/M/src/rem-01.S +++ b/riscv-test-suite/rv64i_m/M/src/rem-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",rem) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",rem) RVTEST_SIGBASE(x1,signature_x1_1) diff --git a/riscv-test-suite/rv64i_m/M/src/remu-01.S b/riscv-test-suite/rv64i_m/M/src/remu-01.S index 81c205c7d..257a73534 100644 --- a/riscv-test-suite/rv64i_m/M/src/remu-01.S +++ b/riscv-test-suite/rv64i_m/M/src/remu-01.S @@ -29,7 +29,7 @@ RVTEST_CODE_BEGIN #ifdef TEST_CASE_1 -RVTEST_CASE(0,"//check ISA:=regex(.*I.*M.*);def TEST_CASE_1=True;",remu) +RVTEST_CASE(0,"//check ISA:=regex(.*RV64.*I.*M.*);def TEST_CASE_1=True;",remu) RVTEST_SIGBASE(x1,signature_x1_1) From b9e5175a980db1e013496c9560a6640823ba32be Mon Sep 17 00:00:00 2001 From: David Harris <74973295+davidharrishmc@users.noreply.github.com> Date: Wed, 15 Nov 2023 07:57:38 -0800 Subject: [PATCH 2/2] Update CHANGELOG.md --- CHANGELOG.md | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index f4eba6546..3946ab9e8 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -1,4 +1,8 @@ # CHANGELOG +## [3.8.2.1] -- 2013-11-15 +- Restored *RV64 Check ISA attributes to RV64IM test \ +cases where they were dropped in 3.8.2. Similar to 3.7.5 + ## [3.8.2] - 2023-11-14 - Added "most negative number divided by -1" case for RV64IM and RV32IM in remw, divw, div and rem tests