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OVPsim with my System Verilog RTL RISCV CPU (RV3i for starters) #17

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weedmank opened this issue Sep 21, 2020 · 0 comments

weedmank commented Sep 21, 2020

I want to be able to have a setup like the diagram shown here:
https://www.imperas.com/articles/imperas-collaborates-with-mentor-on-risc-v-core-rtl-coverage-driven-design-verification

Where is information/videos/tutorials on how to set all this up and what to download and install?

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