Folder organization:
- IP Repo - rfsoc_nrssb/boards/ip/iprepo at main · himanshudutta11/rfsoc_nrssb (github.com)
- TCL scripts : rfsoc_nrssb/boards/RFSoC2x2/rfsoc_nrssb at main · himanshudutta11/rfsoc_nrssb (github.com)
- Bitstream - rfsoc_nrssb/boards/RFSoC2x2/rfsoc_nrssb/bitstream.zip at main · himanshudutta11/rfsoc_nrssb (github.com)
- Python files for PYNQ framesworks - rfsoc_nrssb/rfsoc_nrssb at main · himanshudutta11/rfsoc_nrssb (github.com)
- Jupyter Notebooks - rfsoc_nrssb/notebooks at main · himanshudutta11/rfsoc_nrssb (github.com)
The steps involved:
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Simulink Model – SSB Detect
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HDL Code generation
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IP Core generation
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Block Design and interconnection
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Bitstream generation Bitstream is generated through the script - rfsoc_nrssb/boards/RFSoC2x2/rfsoc_nrssb/make_bitstream.tcl
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Invoking IPs from PYNQ framework