coregen_xil_839584_39.cgp

# Date: Tue May 15 14:37:05 2012

SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc5vlx20t
SET devicefamily = virtex5
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff323
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/

# CRC: e2b133ab