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coregen_xil_839584_39.cgc
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coregen_xil_839584_39.cgc
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<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1.4" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>CoreGen</spirit:library>
<spirit:name>coregen_xil_839584_39</spirit:name>
<spirit:version>1.0</spirit:version>
<spirit:description></spirit:description>
<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen_xil_839584_39</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc5vlx20t</xilinx:device>
<xilinx:deviceFamily>virtex5</xilinx:deviceFamily>
<xilinx:package>ff323</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>VHDL</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>VHDL</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:design>