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Introduce a tiered-1 JIT compiler based on x86-64 architecture
when the using frequency of a block exceeds a predetermined threshold, the baseline tiered1 JIT compiler traces the chained block and generate corresponding low quailty machine code. The resulting target machine code is stored in the code cache for future utilization. The primary objective of introducing the baseline JIT compiler is to enhance the execution speed of RISC-V instructions. This implementation requires two additional components: a tiered1 machine code generator, and code cache. Furthermore, this baseline JIT compiler serves as the foundational target for future improvements. In addition, we have developed a Python script that effectively traces code templates and automatically generates JIT code templates. This approach eliminates the need for manually writing duplicated code. Related: sysprog21#238
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Original file line number | Diff line number | Diff line change |
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@@ -21,3 +21,4 @@ build/path/ | |
tests/**/*.elf | ||
tests/arch-test-target/config.ini | ||
__pycache__/ | ||
src/rv32_jit_template.c |
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