From 33591e9d122ddfcf315b1114f4e9f6795da10e8c Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 6 Aug 2024 13:29:59 +0200 Subject: [PATCH 1/5] Add internal CI and synthesis wrapper --- .github/workflows/gitlab-ci.yml | 29 +++ .gitignore | 4 + .gitlab-ci.yml | 26 +++ Bender.yml | 4 + Makefile | 15 +- src/synth/axi_memory_island_synth.sv | 289 +++++++++++++++++++++++++++ 6 files changed, 366 insertions(+), 1 deletion(-) create mode 100644 .github/workflows/gitlab-ci.yml create mode 100644 .gitlab-ci.yml create mode 100644 src/synth/axi_memory_island_synth.sv diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml new file mode 100644 index 0000000..cdee362 --- /dev/null +++ b/.github/workflows/gitlab-ci.yml @@ -0,0 +1,29 @@ +# Copyright 2022 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Alessandro Ottaviano + +name: gitlab-ci + +on: + push: + branches: [ main ] + pull_request: + branches: [ main ] + workflow_dispatch: + +jobs: + gitlab-ci: + runs-on: ubuntu-latest + steps: + - name: Check Gitlab CI + uses: pulp-platform/pulp-actions/gitlab-ci@v2 + if: > + github.repository == 'pulp-platform/memory_island' && + (github.event_name != 'pull_request' || + github.event.pull_request.head.repo.full_name == github.repository) + with: + domain: iis-git.ee.ethz.ch + repo: github-mirror/memory_island + token: ${{ secrets.GITLAB_TOKEN }} diff --git a/.gitignore b/.gitignore index c9a0c47..6d7b21c 100644 --- a/.gitignore +++ b/.gitignore @@ -8,3 +8,7 @@ work/ transcript vsim.wlf vsim_stacktrace* + +# Internal CI +/nonfree/ +/spyglass/ diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml new file mode 100644 index 0000000..bee44ba --- /dev/null +++ b/.gitlab-ci.yml @@ -0,0 +1,26 @@ +# Copyright 2023 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +# +# Paul Scheffler +# Alessandro Ottaviano + +# We initialize the nonfree repo, then spawn a sub-pipeline from it + +stages: + - nonfree + +init: + stage: nonfree + script: make nonfree-init + artifacts: + paths: [ nonfree/gitlab-ci.yml ] + +subpipe: + stage: nonfree + needs: [ init ] + trigger: + include: + - artifact: nonfree/gitlab-ci.yml + job: init + strategy: depend diff --git a/Bender.yml b/Bender.yml index fcfcaaf..1236c48 100644 --- a/Bender.yml +++ b/Bender.yml @@ -28,3 +28,7 @@ sources: - target: test files: - test/axi_memory_island_tb.sv + + - target: memory_island_standalone_synth + files: + - src/synth/axi_memory_island_synth.sv diff --git a/Makefile b/Makefile index 9ca33b5..5dff3cd 100644 --- a/Makefile +++ b/Makefile @@ -4,7 +4,9 @@ # Michael Rogenmoser -BENDER ?= bender -d $(CURDIR) +MEMORY_ISLAND_ROOT := $(CURDIR) + +BENDER ?= bender -d $(MEMORY_ISLAND_ROOT) VSIM ?= vsim @@ -16,3 +18,14 @@ scripts/compile.tcl: Bender.yml Bender.lock test-vsim: scripts/compile.tcl $(VSIM) -64 -c -do "quit -code [source scripts/compile.tcl]" $(VSIM) -64 -do "vsim axi_memory_island_tb -voptargs=+acc; do scripts/debug_wave.do" + + +## Internal CI +NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/memory_island_nonfree.git +NONFREE_COMMIT ?= master + +nonfree-init: + git clone $(NONFREE_REMOTE) $(MEMORY_ISLAND_ROOT)/nonfree + cd nonfree && git checkout $(NONFREE_COMMIT) + +-include $(MEMORY_ISLAND_ROOT)/nonfree/nonfree.mk diff --git a/src/synth/axi_memory_island_synth.sv b/src/synth/axi_memory_island_synth.sv new file mode 100644 index 0000000..254eead --- /dev/null +++ b/src/synth/axi_memory_island_synth.sv @@ -0,0 +1,289 @@ +// Copyright 2023 ETH Zurich and University of Bologna. +// Internal use only + +// Michael Rogenmoser + +`include "axi/typedef.svh" +`include "axi/port.svh" + +module axi_memory_island_synth #( + localparam int unsigned AddrWidth = 32, + localparam int unsigned NarrowDataWidth = 32, + localparam int unsigned WideDataWidth = 512, + + localparam int unsigned AxiIdWidth = 3, + + localparam int unsigned NumNarrowReq = 5, + localparam int unsigned NumWideReq = 4, + localparam int unsigned WordsPerBank = 8192 +) ( + input logic clk_i, + input logic rst_ni, + + input logic [NumNarrowReq-1:0] s_axi_narrow_awvalid, + input logic [NumNarrowReq-1:0][ AxiIdWidth-1:0] s_axi_narrow_awid, + input logic [NumNarrowReq-1:0][ AddrWidth-1:0] s_axi_narrow_awaddr, + input axi_pkg::len_t [NumNarrowReq-1:0] s_axi_narrow_awlen, + input axi_pkg::size_t [NumNarrowReq-1:0] s_axi_narrow_awsize, + input axi_pkg::burst_t [NumNarrowReq-1:0] s_axi_narrow_awburst, + input logic [NumNarrowReq-1:0] s_axi_narrow_awlock, + input axi_pkg::cache_t [NumNarrowReq-1:0] s_axi_narrow_awcache, + input axi_pkg::prot_t [NumNarrowReq-1:0] s_axi_narrow_awprot, + input axi_pkg::qos_t [NumNarrowReq-1:0] s_axi_narrow_awqos, + input axi_pkg::region_t [NumNarrowReq-1:0] s_axi_narrow_awregion, + input logic [NumNarrowReq-1:0] s_axi_narrow_awuser, + input logic [NumNarrowReq-1:0] s_axi_narrow_wvalid, + input logic [NumNarrowReq-1:0][NarrowDataWidth -1:0] s_axi_narrow_wdata, + input logic [NumNarrowReq-1:0][NarrowDataWidth/8-1:0] s_axi_narrow_wstrb, + input logic [NumNarrowReq-1:0] s_axi_narrow_wlast, + input logic [NumNarrowReq-1:0] s_axi_narrow_wuser, + input logic [NumNarrowReq-1:0] s_axi_narrow_bready, + input logic [NumNarrowReq-1:0] s_axi_narrow_arvalid, + input logic [NumNarrowReq-1:0][ AxiIdWidth-1:0] s_axi_narrow_arid, + input logic [NumNarrowReq-1:0][ AddrWidth-1:0] s_axi_narrow_araddr, + input axi_pkg::len_t [NumNarrowReq-1:0] s_axi_narrow_arlen, + input axi_pkg::size_t [NumNarrowReq-1:0] s_axi_narrow_arsize, + input axi_pkg::burst_t [NumNarrowReq-1:0] s_axi_narrow_arburst, + input logic [NumNarrowReq-1:0] s_axi_narrow_arlock, + input axi_pkg::cache_t [NumNarrowReq-1:0] s_axi_narrow_arcache, + input axi_pkg::prot_t [NumNarrowReq-1:0] s_axi_narrow_arprot, + input axi_pkg::qos_t [NumNarrowReq-1:0] s_axi_narrow_arqos, + input axi_pkg::region_t [NumNarrowReq-1:0] s_axi_narrow_arregion, + input logic [NumNarrowReq-1:0] s_axi_narrow_aruser, + input logic [NumNarrowReq-1:0] s_axi_narrow_rready, + output logic [NumNarrowReq-1:0] s_axi_narrow_awready, + output logic [NumNarrowReq-1:0] s_axi_narrow_arready, + output logic [NumNarrowReq-1:0] s_axi_narrow_wready, + output logic [NumNarrowReq-1:0] s_axi_narrow_bvalid, + output logic [NumNarrowReq-1:0][ AxiIdWidth-1:0] s_axi_narrow_bid, + output axi_pkg::resp_t [NumNarrowReq-1:0] s_axi_narrow_bresp, + output logic [NumNarrowReq-1:0] s_axi_narrow_buser, + output logic [NumNarrowReq-1:0] s_axi_narrow_rvalid, + output logic [NumNarrowReq-1:0][ AxiIdWidth-1:0] s_axi_narrow_rid, + output logic [NumNarrowReq-1:0][NarrowDataWidth -1:0] s_axi_narrow_rdata, + output axi_pkg::resp_t [NumNarrowReq-1:0] s_axi_narrow_rresp, + output logic [NumNarrowReq-1:0] s_axi_narrow_rlast, + output logic [NumNarrowReq-1:0] s_axi_narrow_ruser, + + input logic [NumWideReq-1:0] s_axi_wide_awvalid, + input logic [NumWideReq-1:0][ AxiIdWidth-1:0] s_axi_wide_awid, + input logic [NumWideReq-1:0][ AddrWidth-1:0] s_axi_wide_awaddr, + input axi_pkg::len_t [NumWideReq-1:0] s_axi_wide_awlen, + input axi_pkg::size_t [NumWideReq-1:0] s_axi_wide_awsize, + input axi_pkg::burst_t [NumWideReq-1:0] s_axi_wide_awburst, + input logic [NumWideReq-1:0] s_axi_wide_awlock, + input axi_pkg::cache_t [NumWideReq-1:0] s_axi_wide_awcache, + input axi_pkg::prot_t [NumWideReq-1:0] s_axi_wide_awprot, + input axi_pkg::qos_t [NumWideReq-1:0] s_axi_wide_awqos, + input axi_pkg::region_t [NumWideReq-1:0] s_axi_wide_awregion, + input logic [NumWideReq-1:0] s_axi_wide_awuser, + input logic [NumWideReq-1:0] s_axi_wide_wvalid, + input logic [NumWideReq-1:0][WideDataWidth -1:0] s_axi_wide_wdata, + input logic [NumWideReq-1:0][WideDataWidth/8-1:0] s_axi_wide_wstrb, + input logic [NumWideReq-1:0] s_axi_wide_wlast, + input logic [NumWideReq-1:0] s_axi_wide_wuser, + input logic [NumWideReq-1:0] s_axi_wide_bready, + input logic [NumWideReq-1:0] s_axi_wide_arvalid, + input logic [NumWideReq-1:0][ AxiIdWidth-1:0] s_axi_wide_arid, + input logic [NumWideReq-1:0][ AddrWidth-1:0] s_axi_wide_araddr, + input axi_pkg::len_t [NumWideReq-1:0] s_axi_wide_arlen, + input axi_pkg::size_t [NumWideReq-1:0] s_axi_wide_arsize, + input axi_pkg::burst_t [NumWideReq-1:0] s_axi_wide_arburst, + input logic [NumWideReq-1:0] s_axi_wide_arlock, + input axi_pkg::cache_t [NumWideReq-1:0] s_axi_wide_arcache, + input axi_pkg::prot_t [NumWideReq-1:0] s_axi_wide_arprot, + input axi_pkg::qos_t [NumWideReq-1:0] s_axi_wide_arqos, + input axi_pkg::region_t [NumWideReq-1:0] s_axi_wide_arregion, + input logic [NumWideReq-1:0] s_axi_wide_aruser, + input logic [NumWideReq-1:0] s_axi_wide_rready, + output logic [NumWideReq-1:0] s_axi_wide_awready, + output logic [NumWideReq-1:0] s_axi_wide_arready, + output logic [NumWideReq-1:0] s_axi_wide_wready, + output logic [NumWideReq-1:0] s_axi_wide_bvalid, + output logic [NumWideReq-1:0][ AxiIdWidth-1:0] s_axi_wide_bid, + output axi_pkg::resp_t [NumWideReq-1:0] s_axi_wide_bresp, + output logic [NumWideReq-1:0] s_axi_wide_buser, + output logic [NumWideReq-1:0] s_axi_wide_rvalid, + output logic [NumWideReq-1:0][ AxiIdWidth-1:0] s_axi_wide_rid, + output logic [NumWideReq-1:0][WideDataWidth -1:0] s_axi_wide_rdata, + output axi_pkg::resp_t [NumWideReq-1:0] s_axi_wide_rresp, + output logic [NumWideReq-1:0] s_axi_wide_rlast, + output logic [NumWideReq-1:0] s_axi_wide_ruser + +); + `AXI_TYPEDEF_ALL(axi_narrow, + logic[AddrWidth-1:0], + logic[AxiIdWidth-1:0], + logic[NarrowDataWidth-1:0], + logic[NarrowDataWidth/8-1:0], + logic) + `AXI_TYPEDEF_ALL(axi_wide, + logic[AddrWidth-1:0], + logic[AxiIdWidth-1:0], + logic[WideDataWidth-1:0], + logic[WideDataWidth/8-1:0], + logic) + + axi_narrow_req_t [NumNarrowReq-1:0] narrow_req; + axi_narrow_resp_t [NumNarrowReq-1:0] narrow_rsp; + axi_wide_req_t [NumWideReq -1:0] wide_req; + axi_wide_resp_t [NumWideReq -1:0] wide_rsp; + + axi_narrow_req_t [NumNarrowReq-1:0] narrow_cut_req; + axi_narrow_resp_t [NumNarrowReq-1:0] narrow_cut_rsp; + axi_wide_req_t [NumWideReq -1:0] wide_cut_req; + axi_wide_resp_t [NumWideReq -1:0] wide_cut_rsp; + + for (genvar i = 0; i < NumNarrowReq; i++) begin + assign narrow_req[i].aw_valid = s_axi_narrow_awvalid [i]; + assign narrow_req[i].aw.id = s_axi_narrow_awid [i]; + assign narrow_req[i].aw.addr = s_axi_narrow_awaddr [i]; + assign narrow_req[i].aw.len = s_axi_narrow_awlen [i]; + assign narrow_req[i].aw.size = s_axi_narrow_awsize [i]; + assign narrow_req[i].aw.burst = s_axi_narrow_awburst [i]; + assign narrow_req[i].aw.lock = s_axi_narrow_awlock [i]; + assign narrow_req[i].aw.cache = s_axi_narrow_awcache [i]; + assign narrow_req[i].aw.prot = s_axi_narrow_awprot [i]; + assign narrow_req[i].aw.qos = s_axi_narrow_awqos [i]; + assign narrow_req[i].aw.region = s_axi_narrow_awregion[i]; + assign narrow_req[i].aw.user = s_axi_narrow_awuser [i]; + assign narrow_req[i].w_valid = s_axi_narrow_wvalid [i]; + assign narrow_req[i].w.data = s_axi_narrow_wdata [i]; + assign narrow_req[i].w.strb = s_axi_narrow_wstrb [i]; + assign narrow_req[i].w.last = s_axi_narrow_wlast [i]; + assign narrow_req[i].w.user = s_axi_narrow_wuser [i]; + assign narrow_req[i].b_ready = s_axi_narrow_bready [i]; + assign narrow_req[i].ar_valid = s_axi_narrow_arvalid [i]; + assign narrow_req[i].ar.id = s_axi_narrow_arid [i]; + assign narrow_req[i].ar.addr = s_axi_narrow_araddr [i]; + assign narrow_req[i].ar.len = s_axi_narrow_arlen [i]; + assign narrow_req[i].ar.size = s_axi_narrow_arsize [i]; + assign narrow_req[i].ar.burst = s_axi_narrow_arburst [i]; + assign narrow_req[i].ar.lock = s_axi_narrow_arlock [i]; + assign narrow_req[i].ar.cache = s_axi_narrow_arcache [i]; + assign narrow_req[i].ar.prot = s_axi_narrow_arprot [i]; + assign narrow_req[i].ar.qos = s_axi_narrow_arqos [i]; + assign narrow_req[i].ar.region = s_axi_narrow_arregion[i]; + assign narrow_req[i].ar.user = s_axi_narrow_aruser [i]; + assign narrow_req[i].r_ready = s_axi_narrow_rready [i]; + assign s_axi_narrow_awready[i] = narrow_rsp[i].aw_ready; + assign s_axi_narrow_arready[i] = narrow_rsp[i].ar_ready; + assign s_axi_narrow_wready [i] = narrow_rsp[i].w_ready; + assign s_axi_narrow_bvalid [i] = narrow_rsp[i].b_valid; + assign s_axi_narrow_bid [i] = narrow_rsp[i].b.id; + assign s_axi_narrow_bresp [i] = narrow_rsp[i].b.resp; + assign s_axi_narrow_buser [i] = narrow_rsp[i].b.user; + assign s_axi_narrow_rvalid [i] = narrow_rsp[i].r_valid; + assign s_axi_narrow_rid [i] = narrow_rsp[i].r.id; + assign s_axi_narrow_rdata [i] = narrow_rsp[i].r.data; + assign s_axi_narrow_rresp [i] = narrow_rsp[i].r.resp; + assign s_axi_narrow_rlast [i] = narrow_rsp[i].r.last; + assign s_axi_narrow_ruser [i] = narrow_rsp[i].r.user; + + axi_cut #( + .aw_chan_t ( axi_narrow_aw_chan_t ), + .w_chan_t ( axi_narrow_w_chan_t ), + .b_chan_t ( axi_narrow_b_chan_t ), + .ar_chan_t ( axi_narrow_ar_chan_t ), + .r_chan_t ( axi_narrow_r_chan_t ), + .axi_req_t ( axi_narrow_req_t ), + .axi_resp_t( axi_narrow_resp_t ) + ) i_cut ( + .clk_i, + .rst_ni, + .slv_req_i ( narrow_req [i] ), + .slv_resp_o( narrow_rsp [i] ), + .mst_req_o ( narrow_cut_req[i] ), + .mst_resp_i( narrow_cut_rsp[i] ) + ); + end + + for (genvar i = 0; i < NumWideReq; i++) begin + assign wide_req[i].aw_valid = s_axi_wide_awvalid [i]; + assign wide_req[i].aw.id = s_axi_wide_awid [i]; + assign wide_req[i].aw.addr = s_axi_wide_awaddr [i]; + assign wide_req[i].aw.len = s_axi_wide_awlen [i]; + assign wide_req[i].aw.size = s_axi_wide_awsize [i]; + assign wide_req[i].aw.burst = s_axi_wide_awburst [i]; + assign wide_req[i].aw.lock = s_axi_wide_awlock [i]; + assign wide_req[i].aw.cache = s_axi_wide_awcache [i]; + assign wide_req[i].aw.prot = s_axi_wide_awprot [i]; + assign wide_req[i].aw.qos = s_axi_wide_awqos [i]; + assign wide_req[i].aw.region = s_axi_wide_awregion[i]; + assign wide_req[i].aw.user = s_axi_wide_awuser [i]; + assign wide_req[i].w_valid = s_axi_wide_wvalid [i]; + assign wide_req[i].w.data = s_axi_wide_wdata [i]; + assign wide_req[i].w.strb = s_axi_wide_wstrb [i]; + assign wide_req[i].w.last = s_axi_wide_wlast [i]; + assign wide_req[i].w.user = s_axi_wide_wuser [i]; + assign wide_req[i].b_ready = s_axi_wide_bready [i]; + assign wide_req[i].ar_valid = s_axi_wide_arvalid [i]; + assign wide_req[i].ar.id = s_axi_wide_arid [i]; + assign wide_req[i].ar.addr = s_axi_wide_araddr [i]; + assign wide_req[i].ar.len = s_axi_wide_arlen [i]; + assign wide_req[i].ar.size = s_axi_wide_arsize [i]; + assign wide_req[i].ar.burst = s_axi_wide_arburst [i]; + assign wide_req[i].ar.lock = s_axi_wide_arlock [i]; + assign wide_req[i].ar.cache = s_axi_wide_arcache [i]; + assign wide_req[i].ar.prot = s_axi_wide_arprot [i]; + assign wide_req[i].ar.qos = s_axi_wide_arqos [i]; + assign wide_req[i].ar.region = s_axi_wide_arregion[i]; + assign wide_req[i].ar.user = s_axi_wide_aruser [i]; + assign wide_req[i].r_ready = s_axi_wide_rready [i]; + assign s_axi_wide_awready[i] = wide_rsp[i].aw_ready; + assign s_axi_wide_arready[i] = wide_rsp[i].ar_ready; + assign s_axi_wide_wready [i] = wide_rsp[i].w_ready; + assign s_axi_wide_bvalid [i] = wide_rsp[i].b_valid; + assign s_axi_wide_bid [i] = wide_rsp[i].b.id; + assign s_axi_wide_bresp [i] = wide_rsp[i].b.resp; + assign s_axi_wide_buser [i] = wide_rsp[i].b.user; + assign s_axi_wide_rvalid [i] = wide_rsp[i].r_valid; + assign s_axi_wide_rid [i] = wide_rsp[i].r.id; + assign s_axi_wide_rdata [i] = wide_rsp[i].r.data; + assign s_axi_wide_rresp [i] = wide_rsp[i].r.resp; + assign s_axi_wide_rlast [i] = wide_rsp[i].r.last; + assign s_axi_wide_ruser [i] = wide_rsp[i].r.user; + + axi_cut #( + .aw_chan_t ( axi_wide_aw_chan_t ), + .w_chan_t ( axi_wide_w_chan_t ), + .b_chan_t ( axi_wide_b_chan_t ), + .ar_chan_t ( axi_wide_ar_chan_t ), + .r_chan_t ( axi_wide_r_chan_t ), + .axi_req_t ( axi_wide_req_t ), + .axi_resp_t( axi_wide_resp_t ) + ) i_cut ( + .clk_i, + .rst_ni, + .slv_req_i ( wide_req [i] ), + .slv_resp_o( wide_rsp [i] ), + .mst_req_o ( wide_cut_req[i] ), + .mst_resp_i( wide_cut_rsp[i] ) + ); + end + + axi_memory_island_wrap #( + .AddrWidth ( AddrWidth ), + .NarrowDataWidth ( NarrowDataWidth ), + .WideDataWidth ( WideDataWidth ), + .AxiNarrowIdWidth ( AxiIdWidth ), + .AxiWideIdWidth ( AxiIdWidth ), + .axi_narrow_req_t ( axi_narrow_req_t ), + .axi_narrow_rsp_t ( axi_narrow_resp_t ), + .axi_wide_req_t ( axi_wide_req_t ), + .axi_wide_rsp_t ( axi_wide_resp_t ), + .NumNarrowReq ( NumNarrowReq ), + .NumWideReq ( NumWideReq ), + .WordsPerBank ( WordsPerBank ) + ) i_mem_island ( + .clk_i, + .rst_ni, + + .axi_narrow_req_i ( narrow_cut_req ), + .axi_narrow_rsp_o ( narrow_cut_rsp ), + + .axi_wide_req_i ( wide_cut_req ), + .axi_wide_rsp_o ( wide_cut_rsp ) +); + +endmodule From a139ae9e7be98173bebfa37c59b5a5dc81cd9cef Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 6 Aug 2024 14:14:13 +0200 Subject: [PATCH 2/5] Fix synth wrapper --- src/synth/axi_memory_island_synth.sv | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/synth/axi_memory_island_synth.sv b/src/synth/axi_memory_island_synth.sv index 254eead..d11ab2f 100644 --- a/src/synth/axi_memory_island_synth.sv +++ b/src/synth/axi_memory_island_synth.sv @@ -6,6 +6,7 @@ `include "axi/typedef.svh" `include "axi/port.svh" +// Synthesis wrapper used for testing and internal CI module axi_memory_island_synth #( localparam int unsigned AddrWidth = 32, localparam int unsigned NarrowDataWidth = 32, @@ -31,6 +32,7 @@ module axi_memory_island_synth #( input axi_pkg::prot_t [NumNarrowReq-1:0] s_axi_narrow_awprot, input axi_pkg::qos_t [NumNarrowReq-1:0] s_axi_narrow_awqos, input axi_pkg::region_t [NumNarrowReq-1:0] s_axi_narrow_awregion, + input axi_pkg::atop_t [NumNarrowReq-1:0] s_axi_narrow_awatop, input logic [NumNarrowReq-1:0] s_axi_narrow_awuser, input logic [NumNarrowReq-1:0] s_axi_narrow_wvalid, input logic [NumNarrowReq-1:0][NarrowDataWidth -1:0] s_axi_narrow_wdata, @@ -76,6 +78,7 @@ module axi_memory_island_synth #( input axi_pkg::prot_t [NumWideReq-1:0] s_axi_wide_awprot, input axi_pkg::qos_t [NumWideReq-1:0] s_axi_wide_awqos, input axi_pkg::region_t [NumWideReq-1:0] s_axi_wide_awregion, + input axi_pkg::atop_t [NumWideReq-1:0] s_axi_wide_awatop, input logic [NumWideReq-1:0] s_axi_wide_awuser, input logic [NumWideReq-1:0] s_axi_wide_wvalid, input logic [NumWideReq-1:0][WideDataWidth -1:0] s_axi_wide_wdata, @@ -146,6 +149,7 @@ module axi_memory_island_synth #( assign narrow_req[i].aw.prot = s_axi_narrow_awprot [i]; assign narrow_req[i].aw.qos = s_axi_narrow_awqos [i]; assign narrow_req[i].aw.region = s_axi_narrow_awregion[i]; + assign narrow_req[i].aw.atop = s_axi_narrow_awatop [i]; assign narrow_req[i].aw.user = s_axi_narrow_awuser [i]; assign narrow_req[i].w_valid = s_axi_narrow_wvalid [i]; assign narrow_req[i].w.data = s_axi_narrow_wdata [i]; @@ -210,6 +214,7 @@ module axi_memory_island_synth #( assign wide_req[i].aw.prot = s_axi_wide_awprot [i]; assign wide_req[i].aw.qos = s_axi_wide_awqos [i]; assign wide_req[i].aw.region = s_axi_wide_awregion[i]; + assign wide_req[i].aw.atop = s_axi_wide_awatop [i]; assign wide_req[i].aw.user = s_axi_wide_awuser [i]; assign wide_req[i].w_valid = s_axi_wide_wvalid [i]; assign wide_req[i].w.data = s_axi_wide_wdata [i]; From c26585439ae3962743c477ba79db497b4c08ff6f Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Tue, 6 Aug 2024 15:06:39 +0200 Subject: [PATCH 3/5] Move synth wrapper --- Bender.yml | 2 +- {src => test}/synth/axi_memory_island_synth.sv | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename {src => test}/synth/axi_memory_island_synth.sv (100%) diff --git a/Bender.yml b/Bender.yml index 1236c48..c65d197 100644 --- a/Bender.yml +++ b/Bender.yml @@ -31,4 +31,4 @@ sources: - target: memory_island_standalone_synth files: - - src/synth/axi_memory_island_synth.sv + - test/synth/axi_memory_island_synth.sv diff --git a/src/synth/axi_memory_island_synth.sv b/test/synth/axi_memory_island_synth.sv similarity index 100% rename from src/synth/axi_memory_island_synth.sv rename to test/synth/axi_memory_island_synth.sv From 728cbf96dfe44fafd7140ed01ec64978fd26b31c Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 7 Aug 2024 16:43:38 +0200 Subject: [PATCH 4/5] Fix defaults --- src/axi_memory_island_wrap.sv | 2 +- test/synth/axi_memory_island_synth.sv | 19 ++++++++++++++++--- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/axi_memory_island_wrap.sv b/src/axi_memory_island_wrap.sv index c7c5c35..a73c055 100644 --- a/src/axi_memory_island_wrap.sv +++ b/src/axi_memory_island_wrap.sv @@ -43,7 +43,7 @@ module axi_memory_island_wrap #( parameter int unsigned SpillRspBank = 0, /// Relinquish narrow priority after x cycles, 0 for never. Requires SpillNarrowReqRouted==0. - parameter int unsigned WidePriorityWait = 0, + parameter int unsigned WidePriorityWait = 1, /// Banking Factor for the Wide Ports (power of 2) parameter int unsigned NumWideBanks = (1<<$clog2(NumWideReq))*2*2, diff --git a/test/synth/axi_memory_island_synth.sv b/test/synth/axi_memory_island_synth.sv index d11ab2f..612e7cd 100644 --- a/test/synth/axi_memory_island_synth.sv +++ b/test/synth/axi_memory_island_synth.sv @@ -137,7 +137,7 @@ module axi_memory_island_synth #( axi_wide_req_t [NumWideReq -1:0] wide_cut_req; axi_wide_resp_t [NumWideReq -1:0] wide_cut_rsp; - for (genvar i = 0; i < NumNarrowReq; i++) begin + for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_assign assign narrow_req[i].aw_valid = s_axi_narrow_awvalid [i]; assign narrow_req[i].aw.id = s_axi_narrow_awid [i]; assign narrow_req[i].aw.addr = s_axi_narrow_awaddr [i]; @@ -202,7 +202,7 @@ module axi_memory_island_synth #( ); end - for (genvar i = 0; i < NumWideReq; i++) begin + for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_assign assign wide_req[i].aw_valid = s_axi_wide_awvalid [i]; assign wide_req[i].aw.id = s_axi_wide_awid [i]; assign wide_req[i].aw.addr = s_axi_wide_awaddr [i]; @@ -279,7 +279,20 @@ module axi_memory_island_synth #( .axi_wide_rsp_t ( axi_wide_resp_t ), .NumNarrowReq ( NumNarrowReq ), .NumWideReq ( NumWideReq ), - .WordsPerBank ( WordsPerBank ) + .WordsPerBank ( WordsPerBank ), + .SpillNarrowReqEntry (0), + .SpillNarrowRspEntry (0), + .SpillNarrowReqRouted(0), + .SpillNarrowRspRouted(0), + .SpillWideReqEntry (0), + .SpillWideRspEntry (0), + .SpillWideReqRouted (0), + .SpillWideRspRouted (0), + .SpillWideReqSplit (0), + .SpillWideRspSplit (0), + .SpillReqBank (0), + .SpillRspBank (1), + .WidePriorityWait (2) ) i_mem_island ( .clk_i, .rst_ni, From 70b750aadaa70c4f12018df67d31ae790c0feda1 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Thu, 8 Aug 2024 11:30:31 +0200 Subject: [PATCH 5/5] Add vsim bare test to CI --- Makefile | 3 +++ test/axi_memory_island_tb.sv | 2 +- test/synth/axi_memory_island_synth.sv | 2 +- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index 5dff3cd..c248a01 100644 --- a/Makefile +++ b/Makefile @@ -19,6 +19,9 @@ test-vsim: scripts/compile.tcl $(VSIM) -64 -c -do "quit -code [source scripts/compile.tcl]" $(VSIM) -64 -do "vsim axi_memory_island_tb -voptargs=+acc; do scripts/debug_wave.do" +test-vsim-bare: scripts/compile.tcl + $(VSIM) -64 -c -do "quit -code [source scripts/compile.tcl]" + $(VSIM) -64 -c -do "vsim axi_memory_island_tb; run -all" ## Internal CI NONFREE_REMOTE ?= git@iis-git.ee.ethz.ch:pulp-restricted/memory_island_nonfree.git diff --git a/test/axi_memory_island_tb.sv b/test/axi_memory_island_tb.sv index 99fe8ad..30335a5 100644 --- a/test/axi_memory_island_tb.sv +++ b/test/axi_memory_island_tb.sv @@ -696,7 +696,7 @@ module axi_memory_island_tb #( errors += $countones(mismatch); if (end_of_sim == '1) begin $display("Counted %d errors.", errors); - $stop(); + $finish(errors); end @(posedge clk); end while (1'b1); diff --git a/test/synth/axi_memory_island_synth.sv b/test/synth/axi_memory_island_synth.sv index 612e7cd..3762758 100644 --- a/test/synth/axi_memory_island_synth.sv +++ b/test/synth/axi_memory_island_synth.sv @@ -290,7 +290,7 @@ module axi_memory_island_synth #( .SpillWideRspRouted (0), .SpillWideReqSplit (0), .SpillWideRspSplit (0), - .SpillReqBank (0), + .SpillReqBank (1), .SpillRspBank (1), .WidePriorityWait (2) ) i_mem_island (