From 17994fa4438f9ae6c635b91b37976ea15286b42f Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Fri, 26 Jul 2024 10:27:26 +0200 Subject: [PATCH 1/3] Add initial linting CI --- .github/workflows/lint.yml | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 .github/workflows/lint.yml diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml new file mode 100644 index 0000000..df2a7dd --- /dev/null +++ b/.github/workflows/lint.yml @@ -0,0 +1,29 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +# Author: Michael Rogenmoser + +name: lint + +on: + push: + branches: [ main ] + pull_request: + branches: [ main ] + workflow_dispatch: + +jobs: + lint-verilog: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - uses: chipsalliance/verible-linter-action@main + with: + paths: | + ./src + ./test + exclude_paths: + extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal" + github_token: ${{ secrets.GITHUB_TOKEN }} + reviewdog_reporter: github-check From 69d6f8dfb5f47c6fd9b60c5bceed837ca75af45c Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Fri, 26 Jul 2024 10:56:46 +0200 Subject: [PATCH 2/3] Fix lint --- src/axi_memory_island_wrap.sv | 4 +- src/mem_req_multicut.sv | 6 +- src/mem_rsp_multicut.sv | 6 +- src/memory_island_core.sv | 66 +++++++++++++------ src/varlat_inorder_interco.sv | 96 ++++++++++++++++++--------- test/axi_memory_island_tb.sv | 120 ++++++++++++++++++++-------------- 6 files changed, 190 insertions(+), 108 deletions(-) diff --git a/src/axi_memory_island_wrap.sv b/src/axi_memory_island_wrap.sv index 3afa75e..c7c5c35 100644 --- a/src/axi_memory_island_wrap.sv +++ b/src/axi_memory_island_wrap.sv @@ -63,8 +63,8 @@ module axi_memory_island_wrap #( output axi_wide_rsp_t [ NumWideReq-1:0] axi_wide_rsp_o ); - localparam NarrowStrbWidth = NarrowDataWidth/8; - localparam WideStrbWidth = WideDataWidth/8; + localparam int unsigned NarrowStrbWidth = NarrowDataWidth/8; + localparam int unsigned WideStrbWidth = WideDataWidth/8; logic [2*NumNarrowReq-1:0] narrow_req; logic [2*NumNarrowReq-1:0] narrow_gnt; diff --git a/src/mem_req_multicut.sv b/src/mem_req_multicut.sv index 7ee6ab8..8b2beb5 100644 --- a/src/mem_req_multicut.sv +++ b/src/mem_req_multicut.sv @@ -35,14 +35,14 @@ module mem_req_multicut #( ); localparam int unsigned AggDataWidth = 1+StrbWidth+AddrWidth+DataWidth; - if (NumCuts == 0) begin + if (NumCuts == 0) begin : gen_passthrough assign req_o = req_i; assign gnt_o = gnt_i; assign addr_o = addr_i; assign we_o = we_i; assign wdata_o = wdata_i; assign strb_o = strb_i; - end else begin + end else begin : gen_cuts logic [NumCuts:0][AggDataWidth-1:0] data_agg; logic [NumCuts:0] req, gnt; @@ -53,7 +53,7 @@ module mem_req_multicut #( assign req_o = req [NumCuts]; assign {we_o, strb_o, addr_o, wdata_o} = data_agg[NumCuts]; - for (genvar i = 0; i < NumCuts; i++) begin + for (genvar i = 0; i < NumCuts; i++) begin : gen_cut spill_register #( .T (logic[AggDataWidth-1:0]), .Bypass(1'b0) diff --git a/src/mem_rsp_multicut.sv b/src/mem_rsp_multicut.sv index 370cae6..2e2f23b 100644 --- a/src/mem_rsp_multicut.sv +++ b/src/mem_rsp_multicut.sv @@ -24,11 +24,11 @@ module mem_rsp_multicut #( output logic [DataWidth-1:0] rdata_o ); - if (NumCuts == 0) begin + if (NumCuts == 0) begin : gen_passthrough assign rvalid_o = rvalid_i; assign rready_o = rready_i; assign rdata_o = rdata_i; - end else begin + end else begin : gen_cuts logic [NumCuts:0][DataWidth-1:0] data_agg; logic [NumCuts:0] rvalid, rready; @@ -39,7 +39,7 @@ module mem_rsp_multicut #( assign rvalid_o = rvalid [NumCuts]; assign rdata_o = data_agg [NumCuts]; - for (genvar i = 0; i < NumCuts; i++) begin + for (genvar i = 0; i < NumCuts; i++) begin : gen_cut spill_register #( .T (logic[DataWidth-1:0]), .Bypass(1'b0) diff --git a/src/memory_island_core.sv b/src/memory_island_core.sv index 873cac0..b113673 100644 --- a/src/memory_island_core.sv +++ b/src/memory_island_core.sv @@ -105,7 +105,13 @@ module memory_island_core #( localparam int unsigned NarrowAddrMemWidth = AddrTopBit-AddrNarrowWideBit; localparam int unsigned BankAddrMemWidth = $clog2(WordsPerBank); - localparam int unsigned NarrowIntcBankLat = 1+SpillNarrowReqRouted+SpillNarrowRspRouted+SpillReqBank+SpillRspBank; + localparam int unsigned NarrowIntcBankLat = 1 + + SpillNarrowReqRouted + + SpillNarrowRspRouted + + SpillReqBank + + SpillRspBank; + + localparam int unsigned PriorityWaitWidth = cf_math_pkg::idx_width(WidePriorityWait); logic [ NumNarrowReq-1:0] narrow_req_entry_spill; logic [ NumNarrowReq-1:0] narrow_gnt_entry_spill; @@ -201,8 +207,9 @@ module memory_island_core #( logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowStrbWidth-1:0] strb_bank_spill; logic [ NumWideBanks-1:0][NWDivisor-1:0][ NarrowDataWidth-1:0] rdata_bank_spill; - logic [ NumWideBanks-1:0][NWDivisor-1:0] narrow_priority_req; - logic [ NumWideBanks-1:0][NWDivisor-1:0][cf_math_pkg::idx_width(WidePriorityWait)-1:0] wide_priority_d, wide_priority_q; + logic [ NumWideBanks-1:0][NWDivisor-1:0] narrow_priority_req; + logic [ NumWideBanks-1:0][NWDivisor-1:0][ PriorityWaitWidth-1:0] wide_priority_d, + wide_priority_q; for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_entry_cuts mem_req_multicut #( @@ -365,14 +372,19 @@ module memory_island_core #( // narrow gnt always set assign narrow_gnt_routed_spill = '1; end else begin : gen_narrow_gnt - for (genvar extraFactor = 0; extraFactor < NarrowExtraBF; extraFactor++) begin : gen_narrow_gnt_l1 - for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_gnt_l2 + for (genvar extraFactor = 0; + extraFactor < NarrowExtraBF; + extraFactor++) begin : gen_narrow_gnt_l1 + for (genvar subBank = 0; + subBank < NWDivisor; + subBank++) begin : gen_narrow_gnt_l2 localparam int unsigned PseudoIdx = (extraFactor*NWDivisor) + subBank; always_comb begin narrow_gnt_routed_spill[(extraFactor*NWDivisor) + subBank] = '0; for (int wideBank = 0; wideBank < TotalBanks/WidePseudoBanks; wideBank++) begin if (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank) begin - narrow_gnt_routed_spill[PseudoIdx] = narrow_gnt_bank [(wideBank*NarrowExtraBF)+extraFactor][subBank]; + narrow_gnt_routed_spill[PseudoIdx] = + narrow_gnt_bank [(wideBank*NarrowExtraBF)+extraFactor][subBank]; end end end @@ -381,14 +393,21 @@ module memory_island_core #( end // Route narrow requests to the correct bank, only requesting from the necessary banks - for (genvar wideBank = 0; wideBank < TotalBanks/WidePseudoBanks; wideBank++) begin : gen_narrow_routed_bank_l1 - for (genvar extraFactor = 0; extraFactor < NarrowExtraBF; extraFactor++) begin : gen_narrow_routed_bank_l2 - for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_routed_bank_l3 + for (genvar wideBank = 0; + wideBank < TotalBanks/WidePseudoBanks; + wideBank++) begin : gen_narrow_routed_bank_l1 + for (genvar extraFactor = 0; + extraFactor < NarrowExtraBF; + extraFactor++) begin : gen_narrow_routed_bank_l2 + for (genvar subBank = 0; + subBank < NWDivisor; + subBank++) begin : gen_narrow_routed_bank_l3 localparam int unsigned WideBankIdx = (wideBank*NarrowExtraBF) + extraFactor; localparam int unsigned PseudoIdx = (extraFactor*NWDivisor) + subBank; assign narrow_req_bank [WideBankIdx][subBank] = narrow_req_routed_spill [PseudoIdx] & - (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank); - assign narrow_addr_bank [WideBankIdx][subBank] = narrow_addr_routed_spill [PseudoIdx][NarrowAddrMemWidth-1:NarrowWideBankSelWidth]; + (narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] == wideBank); + assign narrow_addr_bank [WideBankIdx][subBank] = + narrow_addr_routed_spill [PseudoIdx][NarrowAddrMemWidth-1:NarrowWideBankSelWidth]; assign narrow_we_bank [WideBankIdx][subBank] = narrow_we_routed_spill [PseudoIdx]; assign narrow_wdata_bank[WideBankIdx][subBank] = narrow_wdata_routed_spill[PseudoIdx]; assign narrow_strb_bank [WideBankIdx][subBank] = narrow_strb_routed_spill [PseudoIdx]; @@ -397,8 +416,12 @@ module memory_island_core #( end // Shift registers to properly select response data - for (genvar extraFactor = 0; extraFactor < NarrowExtraBF; extraFactor++) begin : gen_narrow_routed_bank_rdata_l1 - for (genvar subBank = 0; subBank < NWDivisor; subBank++) begin : gen_narrow_routed_bank_rdata_l2 + for (genvar extraFactor = 0; + extraFactor < NarrowExtraBF; + extraFactor++) begin : gen_narrow_routed_bank_rdata_l1 + for (genvar subBank = 0; + subBank < NWDivisor; + subBank++) begin : gen_narrow_routed_bank_rdata_l2 localparam int unsigned PseudoIdx = (extraFactor*NWDivisor) + subBank; logic [NarrowWideBankSelWidth-1:0] narrow_rdata_sel; shift_reg #( @@ -410,7 +433,8 @@ module memory_island_core #( .d_i ( narrow_addr_routed_spill [PseudoIdx][NarrowWideBankSelWidth-1:0] ), .d_o ( narrow_rdata_sel ) ); - assign narrow_rdata_routed_spill[PseudoIdx] = narrow_rdata_bank[(narrow_rdata_sel*NarrowExtraBF) + extraFactor][subBank]; + assign narrow_rdata_routed_spill[PseudoIdx] = + narrow_rdata_bank[(narrow_rdata_sel*NarrowExtraBF) + extraFactor][subBank]; end end @@ -594,13 +618,17 @@ module memory_island_core #( end // narrow/wide priority arbitration - assign req_bank [i][j] = narrow_req_bank [i][j] | wide_req_bank_spill[i][j]; + assign req_bank [i][j] = narrow_req_bank [i][j] | wide_req_bank_spill [i][j]; assign narrow_gnt_bank [i][j] = narrow_priority_req[i][j]; assign wide_gnt_bank_spill [i][j] = ~narrow_priority_req[i][j]; - assign we_bank [i][j] = narrow_priority_req[i][j] ? narrow_we_bank [i][j] : wide_we_bank_spill [i][j]; - assign addr_bank [i][j] = narrow_priority_req[i][j] ? narrow_addr_bank [i][j] : wide_addr_bank_spill [i][j]; - assign wdata_bank [i][j] = narrow_priority_req[i][j] ? narrow_wdata_bank[i][j] : wide_wdata_bank_spill[i][j]; - assign strb_bank [i][j] = narrow_priority_req[i][j] ? narrow_strb_bank [i][j] : wide_strb_bank_spill [i][j]; + assign we_bank [i][j] = narrow_priority_req[i][j] ? narrow_we_bank [i][j]: + wide_we_bank_spill [i][j]; + assign addr_bank [i][j] = narrow_priority_req[i][j] ? narrow_addr_bank [i][j]: + wide_addr_bank_spill [i][j]; + assign wdata_bank [i][j] = narrow_priority_req[i][j] ? narrow_wdata_bank [i][j]: + wide_wdata_bank_spill[i][j]; + assign strb_bank [i][j] = narrow_priority_req[i][j] ? narrow_strb_bank [i][j]: + wide_strb_bank_spill [i][j]; assign narrow_rdata_bank [i][j] = rdata_bank [i][j]; assign wide_rdata_bank_spill[i][j] = rdata_bank [i][j]; diff --git a/src/varlat_inorder_interco.sv b/src/varlat_inorder_interco.sv index e8a6fd1..3bf62c0 100644 --- a/src/varlat_inorder_interco.sv +++ b/src/varlat_inorder_interco.sv @@ -7,48 +7,74 @@ module varlat_inorder_interco #( /////////////////////////// // global parameters - parameter int unsigned NumIn = 32, // number of initiator ports (must be aligned with power of 2 for bfly and clos) - parameter int unsigned NumOut = 64, // number of TCDM banks (must be aligned with power of 2 for bfly and clos) - parameter int unsigned AddrWidth = 32, // address width on initiator side - parameter int unsigned DataWidth = 32, // word width of data - parameter int unsigned BeWidth = DataWidth/8, // width of corresponding byte enables - parameter int unsigned AddrMemWidth = 12, // number of address bits per TCDM bank - parameter bit WriteRespOn = 1, // defines whether the interconnect returns a write response + /// number of initiator ports (must be aligned with power of 2 for bfly and clos) + parameter int unsigned NumIn = 32, + /// number of TCDM banks (must be aligned with power of 2 for bfly and clos) + parameter int unsigned NumOut = 64, + /// address width on initiator side + parameter int unsigned AddrWidth = 32, + /// word width of data + parameter int unsigned DataWidth = 32, + /// width of corresponding byte enables + parameter int unsigned BeWidth = DataWidth/8, + /// number of address bits per TCDM bank + parameter int unsigned AddrMemWidth = 12, + /// defines whether the interconnect returns a write response + parameter bit WriteRespOn = 1, + /// Number of outstanding requests supported parameter int unsigned NumOutstanding = 1, - // determines the width of the byte offset in a memory word. normally this can be left at the default vaule, - // but sometimes it needs to be overridden (e.g. when meta-data is supplied to the memory via the wdata signal). + /// determines the width of the byte offset in a memory word. normally this can be left at the + /// default vaule, but sometimes it needs to be overridden (e.g. when meta-data is supplied to + /// the memory via the wdata signal). parameter int unsigned ByteOffWidth = $clog2(DataWidth-1)-3, - // topology can be: LIC, BFLY2, BFLY4, CLOS + /// topology can be: LIC, BFLY2, BFLY4, CLOS parameter tcdm_interconnect_pkg::topo_e Topology = tcdm_interconnect_pkg::LIC, - // number of parallel butterfly's to use, only relevant for BFLY topologies + /// number of parallel butterfly's to use, only relevant for BFLY topologies parameter int unsigned NumPar = 1, - // this detemines which Clos config to use, only relevant for CLOS topologies - // 1: m=0.50*n, 2: m=1.00*n, 3: m=2.00*n + /// this detemines which Clos config to use, only relevant for CLOS topologies + /// 1: m=0.50*n, 2: m=1.00*n, 3: m=2.00*n parameter int unsigned ClosConfig = 2 /////////////////////////// ) ( input logic clk_i, input logic rst_ni, - // master side - input logic [ NumIn-1:0] req_i, // request signal - input logic [ NumIn-1:0][ AddrWidth-1:0] add_i, // tcdm address - input logic [ NumIn-1:0] we_i, // 1: store, 0: load - input logic [ NumIn-1:0][ DataWidth-1:0] wdata_i, // write data - input logic [ NumIn-1:0][ BeWidth-1:0] be_i, // byte enable - output logic [ NumIn-1:0] gnt_o, // grant (combinationally dependent on req_i and add_i - output logic [ NumIn-1:0] vld_o, // response valid, also asserted if write responses ar - output logic [ NumIn-1:0][ DataWidth-1:0] rdata_o, // data response (for load commands) + /// master side + /// request signal + input logic [ NumIn-1:0] req_i, + /// tcdm address + input logic [ NumIn-1:0][ AddrWidth-1:0] add_i, + /// 1: store, 0: load + input logic [ NumIn-1:0] we_i, + /// write data + input logic [ NumIn-1:0][ DataWidth-1:0] wdata_i, + /// byte enable + input logic [ NumIn-1:0][ BeWidth-1:0] be_i, + /// grant (combinationally dependent on req_i and add_i + output logic [ NumIn-1:0] gnt_o, + /// response valid, also asserted if write responses ar + output logic [ NumIn-1:0] vld_o, + /// data response (for load commands) + output logic [ NumIn-1:0][ DataWidth-1:0] rdata_o, // slave side - output logic [NumOut-1:0] req_o, // request out - input logic [NumOut-1:0] gnt_i, // grant input - output logic [NumOut-1:0][AddrMemWidth-1:0] add_o, // address within bank - output logic [NumOut-1:0] we_o, // write enable - output logic [NumOut-1:0][ DataWidth-1:0] wdata_o, // write data - output logic [NumOut-1:0][ BeWidth-1:0] be_o, // byte enable + /// request out + output logic [NumOut-1:0] req_o, + /// grant input + input logic [NumOut-1:0] gnt_i, + /// address within bank + output logic [NumOut-1:0][AddrMemWidth-1:0] add_o, + /// write enable + output logic [NumOut-1:0] we_o, + /// write data + output logic [NumOut-1:0][ DataWidth-1:0] wdata_o, + /// byte enable + output logic [NumOut-1:0][ BeWidth-1:0] be_o, + /// response valid input logic [NumOut-1:0] rvalid_i, + /// response ready output logic [NumOut-1:0] rready_o, - input logic [NumOut-1:0][ DataWidth-1:0] rdata_i // data response (for load commands) + /// data response (for load commands) + input logic [NumOut-1:0][ DataWidth-1:0] rdata_i ); localparam int unsigned NumOutLog2 = $clog2(NumOut); @@ -63,7 +89,11 @@ module varlat_inorder_interco #( // extract bank index assign bank_sel[j] = add_i[j][ByteOffWidth+NumOutLog2-1:ByteOffWidth]; // aggregate data to be routed to slaves - assign data_agg_in[j] = {we_i[j], be_i[j], add_i[j][ByteOffWidth+NumOutLog2+AddrMemWidth-1:ByteOffWidth+NumOutLog2], wdata_i[j]}; + assign data_agg_in[j] = {we_i[j], + be_i[j], + add_i[j][ByteOffWidth+NumOutLog2+AddrMemWidth-1: + ByteOffWidth+NumOutLog2], + wdata_i[j]}; end // disaggregate data @@ -106,7 +136,9 @@ module varlat_inorder_interco #( // Response path for (genvar i = 0; i < NumIn; i++) begin : gen_rsp - assign vld_o[i] = rvalid_i[bank_sel_rsp[i]] & rready_o[bank_sel_rsp[i]] & (ini_addr_rsp[bank_sel_rsp[i]] == i); + assign vld_o[i] = rvalid_i[bank_sel_rsp[i]] & + rready_o[bank_sel_rsp[i]] & + (ini_addr_rsp[bank_sel_rsp[i]] == i); assign rdata_o[i] = rdata_i[bank_sel_rsp[i]]; end for (genvar i = 0; i < NumOut; i++) begin : gen_rready @@ -160,7 +192,7 @@ module varlat_inorder_interco #( .pop_i ( rvalid_i[i] & rready_o[i] ) ); end - end else begin + end else begin : gen_fail $fatal(1, "unimplemented"); end diff --git a/test/axi_memory_island_tb.sv b/test/axi_memory_island_tb.sv index fc86676..99fe8ad 100644 --- a/test/axi_memory_island_tb.sv +++ b/test/axi_memory_island_tb.sv @@ -182,8 +182,8 @@ module axi_memory_island_tb #( int write_len [TotalReq][2**AxiIdWidth]; // Get sizes for debug purposes - for (genvar i = 0; i < TotalReq; i++) begin - for (genvar j = 0; j < 2**AxiIdWidth; j++) begin + for (genvar i = 0; i < TotalReq; i++) begin : gen_len_req + for (genvar j = 0; j < 2**AxiIdWidth; j++) begin : gen_len_axi_id assign read_len[i][j] = $size(regions_being_read[i][j]); assign write_len[i][j] = $size(regions_being_written[i][j]); end @@ -205,7 +205,7 @@ module axi_memory_island_tb #( for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_stim `AXI_ASSIGN_TO_REQ(axi_narrow_req[i], axi_narrow_dv[i]) `AXI_ASSIGN_FROM_RESP(axi_narrow_dv[i], axi_narrow_rsp[i]) - + // Stimuli Generation initial begin narrow_rand_master[i] = new( axi_narrow_dv[i] ); @@ -228,9 +228,11 @@ module axi_memory_island_tb #( for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_limiting // Log address ranges of the requests assign write_range[i].start_addr = axi_narrow_req[i].aw.addr; - assign write_range[i].end_addr = axi_narrow_req[i].aw.addr + ((2**axi_narrow_req[i].aw.size)*(axi_narrow_req[i].aw.len+1)); + assign write_range[i].end_addr = axi_narrow_req[i].aw.addr + + ((2**axi_narrow_req[i].aw.size)*(axi_narrow_req[i].aw.len+1)); assign read_range[i].start_addr = axi_narrow_req[i].ar.addr; - assign read_range[i].end_addr = axi_narrow_req[i].ar.addr + ((2**axi_narrow_req[i].ar.size)*(axi_narrow_req[i].ar.len+1)); + assign read_range[i].end_addr = axi_narrow_req[i].ar.addr + + ((2**axi_narrow_req[i].ar.size)*(axi_narrow_req[i].ar.len+1)); assign aw_hs[i] = filtered_narrow_req[i].aw_valid && axi_narrow_rsp[i].aw_ready; assign ar_hs[i] = filtered_narrow_req[i].ar_valid && axi_narrow_rsp[i].ar_ready; @@ -244,7 +246,9 @@ module axi_memory_island_tb #( // $display("writing to [%x, %x]", write_range[i].start_addr, write_range[i].end_addr); end // pop write queue on B - if (axi_narrow_rsp[i].b_valid && filtered_narrow_req[i].b_ready && axi_narrow_rsp[i].b.id == id) begin + if (axi_narrow_rsp[i].b_valid && + filtered_narrow_req[i].b_ready && + axi_narrow_rsp[i].b.id == id ) begin tmp_write[i] = regions_being_written[i][id].pop_front(); // $display("done writing [%x, %x]",tmp_write[i].start_addr, tmp_write[i].end_addr); end @@ -266,19 +270,25 @@ module axi_memory_island_tb #( for (genvar axiIdx = 0; axiIdx < 2**AxiIdWidth; axiIdx++) begin : gen_overlap_check_ids for (genvar txIdx = 0; txIdx < TxInFlight; txIdx++) begin : gen_overlap_check_txns // Block write if overlapping region is already being written - assign write_overlapping_write[i][requestIdx][axiIdx][txIdx] = txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(write_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; + assign write_overlapping_write[i][requestIdx][axiIdx][txIdx] = + txIdx < write_len[requestIdx][axiIdx] ? + check_overlap(write_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; // Block reads if overlapping region is already being written - assign read_overlapping_write[i][requestIdx][axiIdx][txIdx] = txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(read_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; + assign read_overlapping_write[i][requestIdx][axiIdx][txIdx] = + txIdx < write_len[requestIdx][axiIdx] ? + check_overlap(read_range[i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; // Block write if overlapping region is already being read - assign write_overlapping_read[i][requestIdx][axiIdx][txIdx] = txIdx < read_len[requestIdx][axiIdx] ? - check_overlap(write_range[i], regions_being_read[requestIdx][axiIdx][txIdx]) : '0; + assign write_overlapping_read[i][requestIdx][axiIdx][txIdx] = + txIdx < read_len[requestIdx][axiIdx] ? + check_overlap(write_range[i], regions_being_read[requestIdx][axiIdx][txIdx]) : '0; end end - assign live_write_overlapping_write[i][requestIdx] = check_overlap(write_range[i], write_range[requestIdx]); - assign live_write_overlapping_read[i][requestIdx] = check_overlap(write_range[i], read_range[requestIdx]); - assign live_read_overlapping_write[i][requestIdx] = check_overlap(read_range[i], write_range[requestIdx]); + assign live_write_overlapping_write[i][requestIdx] = + check_overlap(write_range[i], write_range[requestIdx]); + assign live_write_overlapping_read[i][requestIdx] = + check_overlap(write_range[i], read_range[requestIdx]); + assign live_read_overlapping_write[i][requestIdx] = + check_overlap(read_range[i], write_range[requestIdx]); end always_comb begin : proc_filter_narrow @@ -403,32 +413,35 @@ module axi_memory_island_tb #( end for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_limiting + localparam int unsigned ReqIdx = NumNarrowReq+i; // Log address ranges of the requests - assign write_range[NumNarrowReq+i].start_addr = axi_wide_req[i].aw.addr; - assign write_range[NumNarrowReq+i].end_addr = axi_wide_req[i].aw.addr + ((2**axi_wide_req[i].aw.size)*(axi_wide_req[i].aw.len+1)); - assign read_range[NumNarrowReq+i].start_addr = axi_wide_req[i].ar.addr; - assign read_range[NumNarrowReq+i].end_addr = axi_wide_req[i].ar.addr + ((2**axi_wide_req[i].ar.size)*(axi_wide_req[i].ar.len+1)); + assign write_range[ReqIdx].start_addr = axi_wide_req[i].aw.addr; + assign write_range[ReqIdx].end_addr = axi_wide_req[i].aw.addr + + ((2**axi_wide_req[i].aw.size)*(axi_wide_req[i].aw.len+1)); + assign read_range[ReqIdx].start_addr = axi_wide_req[i].ar.addr; + assign read_range[ReqIdx].end_addr = axi_wide_req[i].ar.addr + + ((2**axi_wide_req[i].ar.size)*(axi_wide_req[i].ar.len+1)); - assign aw_hs[NumNarrowReq+i] = filtered_wide_req[i].aw_valid && axi_wide_rsp[i].aw_ready; - assign ar_hs[NumNarrowReq+i] = filtered_wide_req[i].ar_valid && axi_wide_rsp[i].ar_ready; + assign aw_hs[ReqIdx] = filtered_wide_req[i].aw_valid && axi_wide_rsp[i].aw_ready; + assign ar_hs[ReqIdx] = filtered_wide_req[i].ar_valid && axi_wide_rsp[i].ar_ready; // Store in-flight address ranges into a queue always @(posedge clk) begin // push write queue on actual AW - if (aw_hs[NumNarrowReq+i]) begin - regions_being_written[NumNarrowReq+i][axi_wide_req[i].aw.id].push_back(write_range[NumNarrowReq+i]); + if (aw_hs[ReqIdx]) begin + regions_being_written[ReqIdx][axi_wide_req[i].aw.id].push_back(write_range[ReqIdx]); end // pop write queue on B if (axi_wide_rsp[i].b_valid && filtered_wide_req[i].b_ready) begin - tmp_write[NumNarrowReq+i] = regions_being_written[NumNarrowReq+i][axi_wide_rsp[i].b.id].pop_front(); + tmp_write[ReqIdx] = regions_being_written[ReqIdx][axi_wide_rsp[i].b.id].pop_front(); end // push read queue on actual AR - if (ar_hs[NumNarrowReq+i]) begin - regions_being_read[NumNarrowReq+i][axi_wide_req[i].ar.id].push_back(read_range[NumNarrowReq+i]); + if (ar_hs[ReqIdx]) begin + regions_being_read[ReqIdx][axi_wide_req[i].ar.id].push_back(read_range[ReqIdx]); end // pop read queue on last R if (axi_wide_rsp[i].r_valid && filtered_wide_req[i].r_ready && axi_wide_rsp[i].r.last) begin - tmp_read[NumNarrowReq+i] = regions_being_read[NumNarrowReq+i][axi_wide_rsp[i].r.id].pop_front(); + tmp_read[ReqIdx] = regions_being_read[ReqIdx][axi_wide_rsp[i].r.id].pop_front(); end end @@ -436,62 +449,71 @@ module axi_memory_island_tb #( for (genvar axiIdx = 0; axiIdx < 2**AxiIdWidth; axiIdx++) begin : gen_overlap_check_ids for (genvar txIdx = 0; txIdx < TxInFlight; txIdx++) begin : gen_overlap_check_txns // Block write if overlapping region is already being written - assign write_overlapping_write[NumNarrowReq+i][requestIdx][axiIdx][txIdx] = txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(write_range[NumNarrowReq+i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; + assign write_overlapping_write[ReqIdx][requestIdx][axiIdx][txIdx] = + txIdx < write_len[requestIdx][axiIdx] ? + check_overlap(write_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx]): + '0; // Block reads if overlapping region is already being written - assign read_overlapping_write[NumNarrowReq+i][requestIdx][axiIdx][txIdx] = txIdx < write_len[requestIdx][axiIdx] ? - check_overlap(read_range[NumNarrowReq+i], regions_being_written[requestIdx][axiIdx][txIdx]) : '0; + assign read_overlapping_write[ReqIdx][requestIdx][axiIdx][txIdx] = + txIdx < write_len[requestIdx][axiIdx] ? + check_overlap(read_range[ReqIdx], regions_being_written[requestIdx][axiIdx][txIdx]): + '0; // Block write if overlapping region is already being read - assign write_overlapping_read[NumNarrowReq+i][requestIdx][axiIdx][txIdx] = txIdx < read_len[requestIdx][axiIdx] ? - check_overlap(write_range[NumNarrowReq+i], regions_being_read[requestIdx][axiIdx][txIdx]) : '0; + assign write_overlapping_read[ReqIdx][requestIdx][axiIdx][txIdx] = + txIdx < read_len[requestIdx][axiIdx] ? + check_overlap(write_range[ReqIdx], regions_being_read[requestIdx][axiIdx][txIdx]): + '0; end end - assign live_write_overlapping_write[NumNarrowReq+i][requestIdx] = check_overlap(write_range[NumNarrowReq+i], write_range[requestIdx]); - assign live_write_overlapping_read[NumNarrowReq+i][requestIdx] = check_overlap(write_range[NumNarrowReq+i], read_range[requestIdx]); - assign live_read_overlapping_write[NumNarrowReq+i][requestIdx] = check_overlap(read_range[NumNarrowReq+i], write_range[requestIdx]); + assign live_write_overlapping_write[ReqIdx][requestIdx] = + check_overlap(write_range[ReqIdx], write_range[requestIdx]); + assign live_write_overlapping_read[ReqIdx][requestIdx] = + check_overlap(write_range[ReqIdx], read_range[requestIdx]); + assign live_read_overlapping_write[ReqIdx][requestIdx] = + check_overlap(read_range[ReqIdx], write_range[requestIdx]); end always_comb begin : proc_filter_wide // By default connect all signals `AXI_SET_REQ_STRUCT(filtered_wide_req[i], axi_wide_req[i]) `AXI_SET_RESP_STRUCT(axi_wide_rsp[i], filtered_wide_rsp[i]) - blocking_write[NumNarrowReq+i] = '0; - blocking_read[NumNarrowReq+i] = '0; + blocking_write[ReqIdx] = '0; + blocking_read[ReqIdx] = '0; // Block writes if necessary if (axi_wide_req[i].aw_valid && filtered_wide_rsp[i].aw_ready) begin // check in-flight requests - if (|write_overlapping_write[NumNarrowReq+i] || |write_overlapping_read[NumNarrowReq+i]) begin + if (|write_overlapping_write[ReqIdx] || |write_overlapping_read[ReqIdx]) begin filtered_wide_req[i].aw_valid = 1'b0; axi_wide_rsp[i].aw_ready = 1'b0; - blocking_write[NumNarrowReq+i] = 1'b1; + blocking_write[ReqIdx] = 1'b1; end // check other ports - for (int j = 0; j < NumNarrowReq+i; j++) begin + for (int j = 0; j < ReqIdx; j++) begin // Block write if overlapping region is starting to be written by lower ID - if ( (live_write_overlapping_write[NumNarrowReq+i][j] && aw_hs[j]) || - (live_write_overlapping_read [NumNarrowReq+i][j] && ar_hs[j]) ) begin + if ( (live_write_overlapping_write[ReqIdx][j] && aw_hs[j]) || + (live_write_overlapping_read [ReqIdx][j] && ar_hs[j]) ) begin filtered_wide_req[i].aw_valid = 1'b0; axi_wide_rsp[i].aw_ready = 1'b0; - blocking_write[NumNarrowReq+i] = 1'b1; + blocking_write[ReqIdx] = 1'b1; end end end // Block reads if necessary if (axi_wide_req[i].ar_valid && filtered_wide_rsp[i].ar_ready) begin // check in-flight requests - if ( |read_overlapping_write[NumNarrowReq+i] ) begin + if ( |read_overlapping_write[ReqIdx] ) begin filtered_wide_req[i].ar_valid = 1'b0; axi_wide_rsp[i].ar_ready = 1'b0; - blocking_read[NumNarrowReq+i] = 1'b1; + blocking_read[ReqIdx] = 1'b1; end // check other ports - for (int j = 0; j <= NumNarrowReq+i; j++) begin + for (int j = 0; j <= ReqIdx; j++) begin // Block read if overlapping region is starting to be written by lower or same ID - if ( (live_write_overlapping_write[NumNarrowReq+i][j] && aw_hs[j]) ) begin + if ( (live_write_overlapping_write[ReqIdx][j] && aw_hs[j]) ) begin filtered_wide_req[i].ar_valid = 1'b0; axi_wide_rsp[i].ar_ready = 1'b0; - blocking_read[NumNarrowReq+i] = 1'b1; + blocking_read[ReqIdx] = 1'b1; end end end From 0f55253d23ca5fefc6d29e27b88cc26e22bf6b72 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Mon, 29 Jul 2024 13:40:43 +0200 Subject: [PATCH 3/3] Add verible waiver --- .github/verible.waiver | 6 ++++++ .github/workflows/lint.yml | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) create mode 100644 .github/verible.waiver diff --git a/.github/verible.waiver b/.github/verible.waiver new file mode 100644 index 0000000..73a12aa --- /dev/null +++ b/.github/verible.waiver @@ -0,0 +1,6 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +waive --rule=explicit-parameter-storage-type --location="src/memory_island_core.sv" --line=43 +waive --rule=explicit-parameter-storage-type --location="src/axi_memory_island_wrap.sv" --line=54 diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index df2a7dd..f70f3fd 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -24,6 +24,6 @@ jobs: ./src ./test exclude_paths: - extra_args: "--rules=-interface-name-style --lint_fatal --parse_fatal" + extra_args: "--waiver_files .github/verible.waiver --rules=-interface-name-style --lint_fatal --parse_fatal" github_token: ${{ secrets.GITHUB_TOKEN }} reviewdog_reporter: github-check