From 58f7575bff98bf6923d26fd99587d37675602916 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Wed, 7 Aug 2024 16:54:47 +0200 Subject: [PATCH] WIP: add rready wrap --- src/geared_memory_island.sv | 123 ++++++++++++-- src/memory_island_core_rready_wrap.sv | 224 ++++++++++++++++++++++++++ 2 files changed, 335 insertions(+), 12 deletions(-) create mode 100644 src/memory_island_core_rready_wrap.sv diff --git a/src/geared_memory_island.sv b/src/geared_memory_island.sv index 43c6da5..d2771c2 100644 --- a/src/geared_memory_island.sv +++ b/src/geared_memory_island.sv @@ -42,6 +42,8 @@ module geared_memory_island #( parameter int unsigned SpillReqBank = 0, parameter int unsigned SpillRspBank = 0, + parameter bit InternalCombRspReq = 1'b1, + parameter MemorySimInit = "none", // Derived, DO NOT OVERRIDE @@ -94,6 +96,7 @@ module geared_memory_island #( logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_req_geared; logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_gnt_geared; logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_rvalid_geared; + logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_rready_geared; logic [NumNarrowReq-1:0][GearRatio-1:0][NarrowDataWidth-1:0] narrow_rdata_geared; logic [NumNarrowReq-1:0][GearRatio-1:0] narrow_selected; @@ -107,10 +110,16 @@ module geared_memory_island #( logic [GearRatio*NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_wdata_entry_geared; logic [GearRatio*NumNarrowReq-1:0][NarrowStrbWidth-1:0] narrow_strb_entry_geared; logic [GearRatio*NumNarrowReq-1:0] narrow_rvalid_entry_geared; + logic [GearRatio*NumNarrowReq-1:0] narrow_rready_entry_geared; logic [GearRatio*NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_rdata_entry_geared; wide_mem_req_t [NumWideReq-1:0] wide_mem_req; wide_mem_req_t [NumWideReq-1:0][GearRatio-1:0] wide_mem_req_geared; + logic [NumWideReq-1:0][GearRatio-1:0] wide_req_geared; + logic [NumWideReq-1:0][GearRatio-1:0] wide_gnt_geared; + logic [NumWideReq-1:0][GearRatio-1:0] wide_rvalid_geared; + logic [NumWideReq-1:0][GearRatio-1:0] wide_rready_geared; + logic [NumWideReq-1:0][GearRatio-1:0][WideDataWidth-1:0] wide_rdata_geared; logic [GearRatio* NumWideReq-1:0] wide_req_entry_geared; logic [GearRatio* NumWideReq-1:0] wide_gnt_entry_geared; @@ -119,6 +128,7 @@ module geared_memory_island #( logic [GearRatio* NumWideReq-1:0][ WideDataWidth-1:0] wide_wdata_entry_geared; logic [GearRatio* NumWideReq-1:0][ WideStrbWidth-1:0] wide_strb_entry_geared; logic [GearRatio* NumWideReq-1:0] wide_rvalid_entry_geared; + logic [GearRatio* NumWideReq-1:0] wide_rready_entry_geared; logic [GearRatio* NumWideReq-1:0][ WideDataWidth-1:0] wide_rdata_entry_geared; clk_int_div #( @@ -166,14 +176,15 @@ module geared_memory_island #( for (genvar j = 0; j < GearRatio; j++) begin localparam id = i*GearRatio + j; - assign narrow_req_entry_geared [id] = narrow_req_geared [i][j]; - assign narrow_gnt_geared [i][j] = narrow_gnt_entry_geared [id]; - assign narrow_addr_entry_geared [id] = narrow_mem_req_geared [i][j].addr; - assign narrow_we_entry_geared [id] = narrow_mem_req_geared [i][j].we; - assign narrow_wdata_entry_geared[id] = narrow_mem_req_geared [i][j].wdata; - assign narrow_strb_entry_geared [id] = narrow_mem_req_geared [i][j].strb; - assign narrow_rvalid_geared [i][j] = narrow_rvalid_entry_geared[id]; - assign narrow_rdata_geared [i][j] = narrow_rdata_entry_geared [id]; + assign narrow_req_entry_geared [id] = narrow_req_geared [i][j]; + assign narrow_gnt_geared [i][j] = narrow_gnt_entry_geared [id]; + assign narrow_addr_entry_geared [id] = narrow_mem_req_geared [i][j].addr; + assign narrow_we_entry_geared [id] = narrow_mem_req_geared [i][j].we; + assign narrow_wdata_entry_geared [id] = narrow_mem_req_geared [i][j].wdata; + assign narrow_strb_entry_geared [id] = narrow_mem_req_geared [i][j].strb; + assign narrow_rvalid_geared [i][j] = narrow_rvalid_entry_geared[id]; + assign narrow_rready_entry_geared[id] = narrow_rready_geared [i][j]; + assign narrow_rdata_geared [i][j] = narrow_rdata_entry_geared [id]; end onehot_to_bin #( @@ -191,7 +202,7 @@ module geared_memory_island #( .clk_i, .rst_ni, .flush_i ('0), - .testmode_i(), + .testmode_i('0), .full_o (), .empty_o (), .usage_o (), @@ -211,19 +222,103 @@ module geared_memory_island #( .clr_i ('0), .valid_i ( narrow_rvalid_geared [i] ), - .ready_o (), // This is a problem... -> fix it + .ready_o ( narrow_rready_geared [i] ), .data_i ( narrow_rdata_geared [i] ), .valid_o ( narrow_rvalid_o [i] ), .ready_i ( 1'b1 ), .data_o ( narrow_rdata_o [i] ), - .selected_reg_i( 1< + +module memory_island_core_rready_wrap #( + /// Address Width + parameter int unsigned AddrWidth = 0, + /// Data Width for the Narrow Ports + parameter int unsigned NarrowDataWidth = 0, + /// Data Width for the Wide Ports + parameter int unsigned WideDataWidth = 0, + + /// Number of Narrow Ports + parameter int unsigned NumNarrowReq = 0, + /// Number of Wide Ports + parameter int unsigned NumWideReq = 0, + + /// Banking Factor for the Wide Ports (power of 2) + parameter int unsigned NumWideBanks = (1<<$clog2(NumWideReq))*2, + /// Extra multiplier for the Narrow banking factor (baseline is WideWidth/NarrowWidth) (power of 2) + parameter int unsigned NarrowExtraBF = 1, + /// Words per memory bank. (Total number of banks is (WideWidth/NarrowWidth)*NumWideBanks) + parameter int unsigned WordsPerBank = 1024, + + /// Spill Narrow + parameter int unsigned SpillNarrowReqEntry = 0, + parameter int unsigned SpillNarrowRspEntry = 0, + parameter int unsigned SpillNarrowReqRouted = 0, + parameter int unsigned SpillNarrowRspRouted = 0, + /// Spill Wide + parameter int unsigned SpillWideReqEntry = 0, + parameter int unsigned SpillWideRspEntry = 0, + parameter int unsigned SpillWideReqRouted = 0, + parameter int unsigned SpillWideRspRouted = 0, + parameter int unsigned SpillWideReqSplit = 0, + parameter int unsigned SpillWideRspSplit = 0, + /// Spill at Bank + parameter int unsigned SpillReqBank = 0, + parameter int unsigned SpillRspBank = 0, + + parameter bit CombRspReq = 1'b1, + + parameter MemorySimInit = "none", + + /// Relinquish narrow priority after x cycles, 0 for never. Requires SpillNarrowReqRouted==0. + parameter int unsigned WidePriorityWait = 1, + + // Derived, DO NOT OVERRIDE + parameter int unsigned NarrowStrbWidth = NarrowDataWidth/8, + parameter int unsigned WideStrbWidth = WideDataWidth/8, + parameter int unsigned NWDivisor = WideDataWidth/NarrowDataWidth +) ( + input logic clk_i, + input logic rst_ni, + + // Narrow inputs + input logic [NumNarrowReq-1:0] narrow_req_i, + output logic [NumNarrowReq-1:0] narrow_gnt_o, + input logic [NumNarrowReq-1:0][ AddrWidth-1:0] narrow_addr_i, + input logic [NumNarrowReq-1:0] narrow_we_i, + input logic [NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_wdata_i, + input logic [NumNarrowReq-1:0][NarrowStrbWidth-1:0] narrow_strb_i, + output logic [NumNarrowReq-1:0] narrow_rvalid_o, + input logic [NumNarrowReq-1:0] narrow_rready_i, + output logic [NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_rdata_o, + + // Wide inputs + input logic [ NumWideReq-1:0] wide_req_i, + output logic [ NumWideReq-1:0] wide_gnt_o, + input logic [ NumWideReq-1:0][ AddrWidth-1:0] wide_addr_i, + input logic [ NumWideReq-1:0] wide_we_i, + input logic [ NumWideReq-1:0][ WideDataWidth-1:0] wide_wdata_i, + input logic [ NumWideReq-1:0][ WideStrbWidth-1:0] wide_strb_i, + output logic [ NumWideReq-1:0] wide_rvalid_o, + input logic [ NumWideReq-1:0] wide_rready_i, + output logic [ NumWideReq-1:0][ WideDataWidth-1:0] wide_rdata_o +); + + localparam NarrowDepth = ; + localparam WideDepth = ; + + logic [NumNarrowReq-1:0] narrow_req; + logic [NumNarrowReq-1:0] narrow_gnt; + logic [NumNarrowReq-1:0] narrow_rvalid; + logic [NumNarrowReq-1:0][NarrowDataWidth-1:0] narrow_rdata; + logic [NumNarrowReq-1:0] narrow_fifo_ready; + logic [NumNarrowReq-1:0] narrow_credit_left; + + + logic [ NumWideReq-1:0] wide_req; + logic [ NumWideReq-1:0] wide_gnt; + logic [ NumWideReq-1:0] wide_rvalid; + logic [ NumWideReq-1:0][ WideDataWidth-1:0] wide_rdata; + logic [ NumWideReq-1:0] wide_fifo_ready; + logic [ NumWideReq-1:0] wide_credit_left; + + for (genvar i = 0; i < NumNarrowReq; i++) begin : gen_narrow_r_fifo + stream_fifo #( + .FALL_THROUGH ( 1'b1 ), + .DATA_WIDTH ( NarrowDataWidth ), + .DEPTH () + ) i_rdata_fifo ( + .clk_i, + .rst_ni, + .flush_i ('0), + .testmode_i('0), + .usage_o (), + .data_i ( narrow_rdata [i] ), + .valid_i ( narrow_rvalid [i] ), + .ready_o ( narrow_fifo_ready[i] ), + .data_o ( narrow_rdata_o [i] ), + .valid_o ( narrow_rvalid_o [i] ), + .ready_i ( narrow_rready_i [i] ), + ); + + credit_counter #( + .NumCredits ( ), + .InitCreditEmpty( 1'b0 ) + ) i_rdata_credit ( + .clk_i, + .rst_ni, + .credit_o (), + .credit_give_i( narrow_rvalid_o[i] & narrow_rready_i[i] ), + .credit_take_i( narrow_req [i] & narrow_gnt [i] ), + .credit_init_i( '0 ), + .credit_left_o( narrow_credit_left [i] ), + .credit_crit_o(), + .credit_full_o() + ); + + // Only transmit request if we have credits or a space frees up + assign narrow_req [i] = narrow_req_i[i] & (narrow_credit_left[i] | (CombRspReq & narrow_rready_i[i] & narrow_rvalid_o[i])); + // Only grant request if we have credits or a space frees up + assign narrow_gnt_o[i] = narrow_gnt [i] & (narrow_credit_left[i] | (CombRspReq & narrow_rready_i[i] & narrow_rvalid_o[i])); + end + + for (genvar i = 0; i < NumWideReq; i++) begin : gen_wide_r_fifo + stream_fifo #( + .FALL_THROUGH ( 1'b1 ), + .DATA_WIDTH ( WideDataWidth ), + .DEPTH () + ) i_rdata_fifo ( + .clk_i, + .rst_ni, + .flush_i ('0), + .testmode_i('0), + .usage_o (), + .data_i ( wide_rdata [i] ), + .valid_i ( wide_rvalid [i] ), + .ready_o ( wide_fifo_ready[i] ), + .data_o ( wide_rdata_o [i] ), + .valid_o ( wide_rvalid_o [i] ), + .ready_i ( wide_rready_i [i] ), + ); + + credit_counter #( + .NumCredits ( ), + .InitCreditEmpty( 1'b0 ) + ) i_rdata_credit ( + .clk_i, + .rst_ni, + .credit_o (), + .credit_give_i( wide_rvalid_o[i] & wide_rready_i[i] ), + .credit_take_i( wide_req [i] & wide_gnt [i] ), + .credit_init_i( '0 ), + .credit_left_o( wide_credit_left [i] ), + .credit_crit_o(), + .credit_full_o() + ); + + // Only transmit request if we have credits or a space frees up + assign wide_req [i] = wide_req_i[i] & (wide_credit_left[i] | (CombRspReq & wide_rready_i[i] & wide_rvalid_o[i])); + // Only grant request if we have credits or a space frees up + assign wide_gnt_o[i] = wide_gnt [i] & (wide_credit_left[i] | (CombRspReq & wide_rready_i[i] & wide_rvalid_o[i])); + end + + memory_island_core #( + .AddrWidth ( AddrWidth ), + .NarrowDataWidth ( NarrowDataWidth ), + .WideDataWidth ( WideDataWidth ), + .NumNarrowReq ( NumNarrowReq ), + .NumWideReq ( NumWideReq ), + .NumWideBanks ( NumWideBanks ), + .NarrowExtraBF ( NarrowExtraBF ), + .WordsPerBank ( WordsPerBank ), + .SpillNarrowReqEntry ( SpillNarrowReqEntry ), + .SpillNarrowRspEntry ( SpillNarrowRspEntry ), + .SpillNarrowReqRouted ( SpillNarrowReqRouted ), + .SpillNarrowRspRouted ( SpillNarrowRspRouted ), + .SpillWideReqEntry ( SpillWideReqEntry ), + .SpillWideRspEntry ( SpillWideRspEntry ), + .SpillWideReqRouted ( SpillWideReqRouted ), + .SpillWideRspRouted ( SpillWideRspRouted ), + .SpillWideReqSplit ( SpillWideReqSplit ), + .SpillWideRspSplit ( SpillWideRspSplit ), + .SpillReqBank ( SpillReqBank ), + .SpillRspBank ( SpillRspBank ), + .WidePriorityWait ( WidePriorityWait ), + .MemorySimInit ( MemorySimInit ) + ) i_memory_island ( + .clk_i, + .rst_ni, + + .narrow_req_i ( narrow_req ), + .narrow_gnt_o ( narrow_gnt ), + .narrow_addr_i, + .narrow_we_i, + .narrow_wdata_i, + .narrow_strb_i, + .narrow_rvalid_o ( narrow_rvalid ), + .narrow_rdata_o ( narrow_rdata ), + .wide_req_i ( wide_req ), + .wide_gnt_o ( wide_gnt ), + .wide_addr_i, + .wide_we_i, + .wide_wdata_i, + .wide_strb_i, + .wide_rvalid_o ( wide_rvalid ), + .wide_rdata_o ( wide_rdata ) + ); + +endmodule