fusesoc.core

CAPI=2:
name: pulp-platform.org::common_verification:0.2.3

filesets:
  # Files in this package are meant for simulation only.
  simulation:
    files:
      # Source files grouped in levels. Files in level 0 have no dependencies on files in this
      # package. Files in level 1 only depend on files in level 0, files in level 2 on files in
      # levels 1 and 0, etc. Files within a level are ordered alphabetically.
      # Level 0
      - src/clk_rst_gen.sv
      - src/rand_id_queue.sv
      - src/rand_stream_mst.sv
      - src/rand_synch_holdable_driver.sv
      - src/rand_verif_pkg.sv
      - src/signal_highlighter.sv
      - src/sim_timeout.sv
      - src/stream_watchdog.sv
      # Level 1
      - src/rand_synch_driver.sv
      # Level 2
      - src/rand_stream_slv.sv
    file_type : systemVerilogSource

  bench:
    files:
      - test/tb_clk_rst_gen.sv
    file_type : systemVerilogSource
targets:
  default:
    filesets : [simulation]