From 9a53b3c66d32725e5c5656b02e1caf07c5f79a97 Mon Sep 17 00:00:00 2001 From: Thomas Benz Date: Thu, 1 Sep 2022 10:00:24 +0200 Subject: [PATCH] Release v0.37.0 --- CHANGELOG.md | 26 ++++++++++++++++++++++---- README.md | 3 +++ VERSION | 2 +- axi.core | 2 +- ips_list.yml | 4 ++++ 5 files changed, 31 insertions(+), 6 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 5e46abaf0..a7e88501a 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -8,25 +8,43 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0. ## Unreleased ### Added -- `axi_to_mem`: AXI4+ATOP slave to control on chip memory. + +### Changed + +### Fixed + + +## 0.37.0 - 2022-08-30 + +### Added +- `axi_fifo`: Inserts a FIFO into all 5 AXI4 channels; add module and its testbench - `axi_test`: Add `mapped` mode to the random classes as well as additional functionality to the scoreboard class. - `axi_throttle`: Add a module that limits the maximum number of outstanding transfers sent to the downstream logic. +- `axi_to_mem`: AXI4+ATOP slave to control on chip memory. - `axi_to_mem_banked`: AXI4+ATOP slave to control on chip memory, with banking support, higher - throughput than `axi_to_mem`. + throughput than `axi_to_mem`. - `axi_to_mem_interleaved`: AXI4+ATOP slave to control on chip memory, interleaved to prevent - deadlocks. + deadlocks. - `axi_to_mem_split`: AXI4+ATOP slave to control memory protocol interconnect. - `Bender`: Add dependency `tech_cells_generic` `v0.2.2` for generic SRAM macro for simulation. ### Changed +- `axi_demux`: Add module docstring +- `axi_sim_mem`: Add the capability to emit read and write errors +- `Bender`: Update dependency `common_cells` to `v1.26.0` from `v1.21.0` (required by + `axi_throttle`) +- Remove `docs` directory, move content to `doc` folder. `docs` is automatically created and + populated during the CI run. +- Update vsim version to `2021.3` in CI, drop test for `2020.1` and `2021.1` ### Fixed +- `axi_lite_demux`: Improve compatibility with vsim version 10.7b. - `axi_lite_mux`: Reduce complexity of W channel at master port by removing an unnecessary multiplexer. -- `axi_lite_demux`: Improve compatibility with vsim version 10.7b. +`v0.37.0` is fully **backward-compatible** to `v0.36.0`. ## 0.36.0 - 2022-07-07 diff --git a/README.md b/README.md index b26d3ae6c..5daef26f8 100644 --- a/README.md +++ b/README.md @@ -101,6 +101,9 @@ We aim to be compatible with a wide range of EDA tools. For this reason, we str - the workaround does not break functionality in other tools, and - the workaround does not significantly complicate code or add maintenance overhead. +In addition, we suggest to report issues with the SystemVerilog language support directly to the EDA vendor. Our code is fully open and +can / should be shared with the EDA vendor as a testcase for any language problem encountered. + All code in each release and on the default branch is tested on a recent version of at least one industry-standard RTL simulator and synthesizer. You can examine the [CI settings](./.gitlab-ci.yml) to find out which version of which tool we are running. diff --git a/VERSION b/VERSION index 66ca32f1b..0f1a7dfc7 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -0.36.1-dev +0.37.0 diff --git a/axi.core b/axi.core index 711a08e9c..49e39886a 100644 --- a/axi.core +++ b/axi.core @@ -1,6 +1,6 @@ CAPI=2: -name : pulp-platform.org::axi:0.36.1-dev +name : pulp-platform.org::axi:0.37.0 filesets: rtl: diff --git a/ips_list.yml b/ips_list.yml index 7056ebac2..c7dad06ac 100644 --- a/ips_list.yml +++ b/ips_list.yml @@ -5,3 +5,7 @@ common_cells: common_verification: commit: v0.2.0 group: pulp-platform + +tech_cells_generic: + commit: v0.2.2 + group: pulp-platform