PyUVM RAL

[SikoVerilog]

Hello,

There is a one more way to use UVM is PyUVM. Where we need a uvm_ral model for RAL test and verification that is almost equal to the systemverilog uvm_ral but in python syntax. I think every pyuvm user need this to test and program the RAL.

If any one have any comment on that kindly share

Thanks

[taichi-ishitani]

You can implement PyUVM RAL support as a plugin.
This wiki describes how to create a plugin.
https://github.com/rggen/rggen/wiki/Create-Your-Own-Plugin

In addition, the SV RAL generator is implmeneted as a plugin so you can refer its implementation when you implement PyUVM RAL support.
https://github.com/rggen/rggen-systemverilog/blob/master/lib/rggen/systemverilog/ral.rb
https://github.com/rggen/rggen-systemverilog/blob/master/lib/rggen/systemverilog/ral