Unable to read FIC1 memory on polarfire soc #410
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ASAexo38
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Applications and demos
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Can you make sure the reset is released and clock is enabled for FIC1? There is an example here using the HAL APIs to do this dma example FIC 1 is used in the Icicle Kit reference design for PCIe and DMA which are tested so its more than likely just a reset issue :) |
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Hi , I'm facing the same problem, did you find the solution please ? |
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Hello
We are faced to a problem with the polarfire soc.
We are using enclustra kit Mercury+ MP1
We are trying to implement the AXI4 through the Fabric Interface Controller (FIC) (see picture below for schematic)
FIC3 is working fine but this one is directly connected to the AXI switch.
FIC1 accesses are totally blocking the serial interface. (reading to the memory address 0xE0000000 which corresponds to the FIC1)
So we could not find the way to communicate using the FIC1.
FIC1 is selected as an initiator in the MSS configurator.
We saw that MPU is the only thing in the way of the FIC, but normally, not touching the MPU would allow the accesses of all the memory parts.
We do not know if we need to create MPU or if just by disabling it we get access to the memory of the FIC1.
Inside the FPGA, AXI4 signals such as in the picture 'axi-read.png'
Signal are, top to bottom these
MSS FIC1:
RLAST
RVALID
RREADY
ARREADY
ARVALID
SLAVE1:
RREADY
RVALID
RLAST
ARVALID
ARREADY
I also attached the configuration of the axi_interconnect. All signals here are connected to output pins directly in the hdl ('axi4_interconnect.txt' which is actually a .tcl file but I could not upload it with the right extension here)
We do not succeed to access FIC1 and we do not have anymore ideas to get it work.
Even worse, when we are trying to get memory valu, the serial port (MMUART1) is crashing.
Do you have any clue about this problem ?
Thanks for your help,
Regards
axi4_interconnect .txt
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