AUC Open Source Hardware Lab

All

23 repositories

Fault
Public
A complete open-source design-for-testing (DFT) Solution
testing dft eda verilog verilog-hdl jtag atpg fault-simulation vlsi-cad scan-chains
Swift
•
Apache License 2.0
•30•143•9•1•Updated Nov 2, 2024Nov 2, 2024
Lighter
Public
An automatic clock gating utility
Verilog
•
Apache License 2.0
•5•43•3•0•Updated Jul 16, 2024Jul 16, 2024
DFFRAM
Public
Standard Cell Library based Memory Compiler using FF/Latch cells
verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design
Verilog
•
Apache License 2.0
•33•137•27•4•Updated Jun 15, 2024Jun 15, 2024
RTL-Repo
Public
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24
verilog rtl-design llm llm-benchmarking
Python
•
Apache License 2.0
•0•5•0•0•Updated Jun 5, 2024Jun 5, 2024
Stdcells
Public
The Standard Cell Libraries Used By The Cloud V Platform
Verilog
•1•1•0•0•Updated Mar 17, 2023Mar 17, 2023
sky130-builds
Public archive
What it says on the tin
Python
•1•4•0•0•Updated Apr 26, 2022Apr 26, 2022
spef-extractor
Public archive
A Python library that reads LEF and DEF files, extract the RC parasitics and generate their corresponding SPEF file.
Python
•
Apache License 2.0
•8•7•0•0•Updated Apr 1, 2022Apr 1, 2022
homebrew-icestorm
Public
Homebrew tap for Icestorm.
Ruby
•
BSD 2-Clause "Simplified" License
•2•4•1•0•Updated Nov 17, 2021Nov 17, 2021
Documentation
Public
This repository hosts the documentation for Cloud V.
0•1•0•0•Updated Jul 8, 2021Jul 8, 2021
vcd-parser
Public
VCD Parser for Node.js
JavaScript
•
MIT License
•3•2•0•0•Updated Jul 3, 2021Jul 3, 2021
Opendbpy
Public archive
Verilog
•
Other
•576•0•0•0•Updated Jun 2, 2021Jun 2, 2021
dffram-env
Public archive
Dockerfile with a ready environment to run placeRAM.py in DFFRAM
Dockerfile
•0•0•0•0•Updated May 18, 2021May 18, 2021
icestorm-builder
Public
Builds binaries for FPGA Icestorm
Dockerfile
•
The Unlicense
•1•0•0•0•Updated Apr 10, 2021Apr 10, 2021
Classic-Playground
Public archive
A playground based on the classic version of the Cloud V IDE
eda verilog verilog-hdl verilog-simulator online-ide
JavaScript
•
Apache License 2.0
•1•3•0•2•Updated Mar 23, 2021Mar 23, 2021
Cloud-V.github.io
Public
Github Pages template for academic personal websites, forked from mmistakes/minimal-mistakes
JavaScript
•
MIT License
•45k•0•0•0•Updated Feb 1, 2021Feb 1, 2021
OGRE
Public
Global Router Built for ICCAD Contest 2019
asic vlsi router lef lef-def-parser
C++
•
GNU General Public License v3.0
•13•30•1•1•Updated Mar 20, 2020Mar 20, 2020
Pollen
Public archive
SoC JSON to RTL generator.
TypeScript
•
GNU General Public License v3.0
•1•1•0•0•Updated Feb 9, 2020Feb 9, 2020
Redesign-Concept
Public archive
Early redesign concept
HTML
•
MIT License
•0•0•2•0•Updated Sep 11, 2019Sep 11, 2019
beekeeper-webui
Public archive
Web UI for Beekeeper (Unreleased Project)
JavaScript
•
GNU General Public License v3.0
•0•0•1•0•Updated Nov 6, 2018Nov 6, 2018
Malice
Public archive
GTK interface for iceprog, with (most) batteries included.
C
•
GNU General Public License v3.0
•0•1•0•0•Updated Nov 6, 2018Nov 6, 2018
dwarfRV32
Public
A small footprint pipelined implementation of RV32i.
Verilog
•
GNU General Public License v3.0
•2•5•0•0•Updated Feb 21, 2018Feb 21, 2018
tneo
Public archive
A port of the TNeo kernel to the dwarfRV32 CPU.
C
•
Apache License 2.0
•49•0•0•0•Updated Feb 21, 2018Feb 21, 2018
FreeRTOS
Public archive
Port of FreeRTOS for dwarfRV32.
C
•
Other
•42•0•0•0•Updated Feb 21, 2018Feb 21, 2018