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Some typos updates following #863 feedback.
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Signed-off-by: Pascal Gouedo <[email protected]>
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Pascal Gouedo committed Sep 1, 2023
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Showing 1 changed file with 11 additions and 11 deletions.
22 changes: 11 additions & 11 deletions docs/source/instruction_set_extensions.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -672,19 +672,19 @@ Bit Manipulation Encoding
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 31: 30 | 29 : 25 | 24 : 20 | 19 : 15 | 14 : 12 | 11 : 7 | 6 : 0 | |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| **f2** | **ls3[4:0]** | **ls2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** |
| **f2** | **Is3[4:0]** | **Is2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | **Mnemonic** |
+========+======================+===============+=========+============+========+============+====================================+
| 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extract rD, rs1, Is3, Is2** |
| 00 | Luimm5[4:0] | Luimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extract rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extractu rD, rs1, Is3, Is2** |
| 01 | Luimm5[4:0] | Luimm5[4:0] | src | 000 | dest | 101 1011 | **cv.extractu rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 10 | Luimm5[4:0] | Iuimm5[4:0] | src | 000 | dest | 101 1011 | **cv.insert rD, rs1, Is3, Is2** |
| 10 | Luimm5[4:0] | Luimm5[4:0] | src | 000 | dest | 101 1011 | **cv.insert rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 00 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bclr rD, rs1, Is3, Is2** |
| 00 | Luimm5[4:0] | Luimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bclr rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 01 | Luimm5[4:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bset rD, rs1, Is3, Is2** |
| 01 | Luimm5[4:0] | Luimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bset rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+
| 11 | 000, Luimm2[1:0] | Iuimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bitrev rD, rs1, Is3, Is2** |
| 11 | 000, Luimm2[1:0] | Luimm5[4:0] | src | 001 | dest | 101 1011 | **cv.bitrev rD, rs1, Is3, Is2** |
+--------+----------------------+---------------+---------+------------+--------+------------+------------------------------------+

.. table:: Register Bit Manipulation operations encoding
Expand Down Expand Up @@ -771,7 +771,7 @@ General ALU operations
| | |
| | else rD = rs1 |
| | |
| | Note: If ls2 is equal to 0, |
| | Note: If Is2 is equal to 0, |
| | |
| | -2^(Is2-1) is equivalent to -1 while (2^(Is2-1)-1) is equivalent to 0. |
+-------------------------------------------+------------------------------------------------------------------------+
Expand All @@ -781,7 +781,7 @@ General ALU operations
| | |
| | else rD = rs1 |
| | |
| | Note: If ls2 is equal to 0, (2^(Is2-1)-1) is equivalent to 0. |
| | Note: If Is2 is equal to 0, (2^(Is2-1)-1) is equivalent to 0. |
+-------------------------------------------+------------------------------------------------------------------------+
| **cv.clipr rD, rs1, rs2** | if rs1 <= -(rs2+1), rD = -(rs2+1), |
| | |
Expand Down Expand Up @@ -926,9 +926,9 @@ General ALU Encoding
+------------+---------------+---------+------------+--------+------------+-----------------------------+
| **funct7** | **Is2[4:0]** | **rs1** | **funct3** | **rD** | **opcode** | |
+============+===============+=========+============+========+============+=============================+
| 011 1000 | Iuimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clip rD, rs1, Is2** |
| 011 1000 | Luimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clip rD, rs1, Is2** |
+------------+---------------+---------+------------+--------+------------+-----------------------------+
| 011 1001 | Iuimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clipu rD, rs1, Is2** |
| 011 1001 | Luimm5[4:0] | src1 | 011 | dest | 010 1011 | **cv.clipu rD, rs1, Is2** |
+------------+---------------+---------+------------+--------+------------+-----------------------------+
| 011 1010 | src2 | src1 | 011 | dest | 010 1011 | **cv.clipr rD, rs1, rs2** |
+------------+---------------+---------+------------+--------+------------+-----------------------------+
Expand Down

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