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[BUG] : mip.MSIP and mie.MSIE are read-only zeros #2531

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AyoubJalali opened this issue Sep 12, 2024 · 2 comments
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[BUG] : mip.MSIP and mie.MSIE are read-only zeros #2531

AyoubJalali opened this issue Sep 12, 2024 · 2 comments
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@zchamski
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Spike Tandem

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@AyoubJalali
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According to CV32A65X Spec, As the system has only one hart then mip.MSIP and mie.MSIE are read-only zeros.

So there's a bug on Spike (solo and tandem), it allow modifying mip.MSIP and mie.MSIE
@AyoubJalali AyoubJalali mentioned this issue Sep 13, 2024
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@zchamski
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After locally updating the mask/override/init parameters in Spike Yaml config of CV32A65X the behavior is as per specification, duly exposing the CVA6 RTL issue (openhwgroup/cva6#2500).

@AyoubJalali
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Fixed by openhwgroup/cva6#2523
Thanks to @zchamski

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