From cb2b643abf5f7edeaa03abc7536e99680122b3b5 Mon Sep 17 00:00:00 2001 From: Henrik Fegran Date: Tue, 3 Oct 2023 15:40:08 +0200 Subject: [PATCH] Fixed isacov rd/rs-issues for zb* instructions (ISA_DECODER only) Signed-off-by: Henrik Fegran --- lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv b/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv index e04d55df88..42ed90a75d 100644 --- a/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv +++ b/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv @@ -329,7 +329,13 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL endcase end - mon_trn.instr.set_valid_flags(); + if (cfg.decoder == SPIKE) begin + mon_trn.instr.set_valid_flags(); + end else begin // if ISA_DECODER + mon_trn.instr.rd_valid = instr_asm.rd.valid; + mon_trn.instr.rs1_valid = instr_asm.rs1.valid; + mon_trn.instr.rs2_valid = instr_asm.rs2.valid; + end // Set enumerations for register values as reported from RVFI if (mon_trn.instr.rs1_valid) begin