From ad20a21f8b296d21d1fc7ea97dac2a2170138b20 Mon Sep 17 00:00:00 2001 From: openfpga-admin Date: Fri, 29 Jul 2022 09:35:30 +0100 Subject: [PATCH] v1.0.0 --- README.md | 7 + audio.json | 5 + core.json | 34 + data.json | 6 + input.json | 6 + interact.json | 7 + output/.gitkeep | 0 output/assets/.keep | 0 output/bitstream.rbf_r | Bin 0 -> 788108 bytes src/fpga/.gitignore | 28 + src/fpga/ap_core.qpf | 31 + src/fpga/ap_core.qsf | 748 +++++++++++ src/fpga/apf/apf.qip | 7 + src/fpga/apf/apf_constraints.sdc | 20 + src/fpga/apf/apf_top.v | 471 +++++++ src/fpga/apf/build_id.mif | 16 + src/fpga/apf/build_id_gen.tcl | 171 +++ src/fpga/apf/common.v | 152 +++ src/fpga/apf/io_bridge_peripheral.v | 332 +++++ src/fpga/apf/io_pad_controller.v | 324 +++++ src/fpga/apf/mf_datatable.qip | 4 + src/fpga/apf/mf_datatable.v | 247 ++++ src/fpga/apf/mf_ddio_bidir_12.qip | 5 + src/fpga/apf/mf_ddio_bidir_12.v | 134 ++ src/fpga/core/core_bridge_cmd.v | 435 +++++++ src/fpga/core/core_constraints.sdc | 14 + src/fpga/core/core_top.v | 562 ++++++++ src/fpga/core/mf_pllbase.bsf | 126 ++ src/fpga/core/mf_pllbase.ppf | 17 + src/fpga/core/mf_pllbase.qip | 337 +++++ src/fpga/core/mf_pllbase.sip | 6 + src/fpga/core/mf_pllbase.spd | 6 + src/fpga/core/mf_pllbase.v | 261 ++++ src/fpga/core/mf_pllbase/mf_pllbase_0002.qip | 4 + src/fpga/core/mf_pllbase/mf_pllbase_0002.v | 99 ++ src/fpga/core/mf_pllbase_sim.f | 1 + .../mf_pllbase_sim/aldec/rivierapro_setup.tcl | 278 ++++ src/fpga/core/mf_pllbase_sim/cadence/cds.lib | 19 + src/fpga/core/mf_pllbase_sim/cadence/hdl.var | 2 + .../mf_pllbase_sim/cadence/ncsim_setup.sh | 195 +++ .../core/mf_pllbase_sim/mentor/msim_setup.tcl | 272 ++++ src/fpga/core/mf_pllbase_sim/mf_pllbase.vo | 309 +++++ .../mf_pllbase_sim/synopsys/vcs/vcs_setup.sh | 152 +++ .../synopsys/vcsmx/synopsys_sim.setup | 13 + .../synopsys/vcsmx/vcsmx_setup.sh | 195 +++ src/fpga/core/pin_ddio_clk.ppf | 11 + src/fpga/core/pin_ddio_clk.qip | 6 + src/fpga/core/pin_ddio_clk.v | 108 ++ src/fpga/core/stp1.stp | 1135 +++++++++++++++++ src/fpga/output_files/.gitignore | 2 + src/fpga/output_files/ap_core.jdi | 8 + src/fpga/output_files/ap_core.rbf | Bin 0 -> 788528 bytes src/fpga/output_files/ap_core.sof | Bin 0 -> 2451335 bytes variants.json | 6 + video.json | 15 + 55 files changed, 7349 insertions(+) create mode 100644 README.md create mode 100644 audio.json create mode 100644 core.json create mode 100644 data.json create mode 100644 input.json create mode 100644 interact.json create mode 100644 output/.gitkeep create mode 100644 output/assets/.keep create mode 100644 output/bitstream.rbf_r create mode 100644 src/fpga/.gitignore create mode 100644 src/fpga/ap_core.qpf create mode 100644 src/fpga/ap_core.qsf create mode 100644 src/fpga/apf/apf.qip create mode 100644 src/fpga/apf/apf_constraints.sdc create mode 100644 src/fpga/apf/apf_top.v create mode 100644 src/fpga/apf/build_id.mif create mode 100644 src/fpga/apf/build_id_gen.tcl create mode 100644 src/fpga/apf/common.v create mode 100644 src/fpga/apf/io_bridge_peripheral.v create mode 100644 src/fpga/apf/io_pad_controller.v create mode 100644 src/fpga/apf/mf_datatable.qip create mode 100644 src/fpga/apf/mf_datatable.v create mode 100644 src/fpga/apf/mf_ddio_bidir_12.qip create mode 100644 src/fpga/apf/mf_ddio_bidir_12.v create mode 100644 src/fpga/core/core_bridge_cmd.v create mode 100644 src/fpga/core/core_constraints.sdc create mode 100644 src/fpga/core/core_top.v create mode 100644 src/fpga/core/mf_pllbase.bsf create mode 100644 src/fpga/core/mf_pllbase.ppf create mode 100644 src/fpga/core/mf_pllbase.qip create mode 100644 src/fpga/core/mf_pllbase.sip create mode 100644 src/fpga/core/mf_pllbase.spd create mode 100644 src/fpga/core/mf_pllbase.v create mode 100644 src/fpga/core/mf_pllbase/mf_pllbase_0002.qip create mode 100644 src/fpga/core/mf_pllbase/mf_pllbase_0002.v create mode 100644 src/fpga/core/mf_pllbase_sim.f create mode 100644 src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl create mode 100644 src/fpga/core/mf_pllbase_sim/cadence/cds.lib create mode 100644 src/fpga/core/mf_pllbase_sim/cadence/hdl.var create mode 100644 src/fpga/core/mf_pllbase_sim/cadence/ncsim_setup.sh create mode 100644 src/fpga/core/mf_pllbase_sim/mentor/msim_setup.tcl create mode 100644 src/fpga/core/mf_pllbase_sim/mf_pllbase.vo create mode 100644 src/fpga/core/mf_pllbase_sim/synopsys/vcs/vcs_setup.sh create mode 100644 src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/synopsys_sim.setup create mode 100644 src/fpga/core/mf_pllbase_sim/synopsys/vcsmx/vcsmx_setup.sh create mode 100644 src/fpga/core/pin_ddio_clk.ppf create mode 100644 src/fpga/core/pin_ddio_clk.qip create mode 100644 src/fpga/core/pin_ddio_clk.v create mode 100644 src/fpga/core/stp1.stp create mode 100644 src/fpga/output_files/.gitignore create mode 100644 src/fpga/output_files/ap_core.jdi create mode 100644 src/fpga/output_files/ap_core.rbf create mode 100644 src/fpga/output_files/ap_core.sof create mode 100644 variants.json create mode 100644 video.json diff --git a/README.md b/README.md new file mode 100644 index 0000000..e693664 --- /dev/null +++ b/README.md @@ -0,0 +1,7 @@ +# Core Template +This is a template repository for a core which contains all of the core definition JSON files and FPGA starter code. + +## Legal +Analogue’s Development program was created to further video game hardware preservation with FPGA technology. Analogue does not support or endorse the use of infringing content. + +Analogue Developers have access to Analogue Pocket I/O’s so Developers can utilize cartridge adapters or interface with other pieces of original or bespoke hardware to support legacy media. diff --git a/audio.json b/audio.json new file mode 100644 index 0000000..31d0516 --- /dev/null +++ b/audio.json @@ -0,0 +1,5 @@ +{ + "audio": { + "magic": "APF_VER_1" + } +} \ No newline at end of file diff --git a/core.json b/core.json new file mode 100644 index 0000000..bc25e9a --- /dev/null +++ b/core.json @@ -0,0 +1,34 @@ +{ + "core": { + "magic": "APF_VER_1", + "metadata": { + "platform_ids": [], + "shortname": "template", + "description": "Core template. Displays gray test screen.", + "author": "Developer", + "url": "https://github.com/open-fpga/core-template", + "version": "1.0", + "date_release": "2022-06-30" + }, + "framework": { + "target_product": "Analogue Pocket", + "version_required": "1.1", + "sleep_supported": false, + "dock": { + "supported": true, + "analog_output": false + }, + "hardware": { + "link_port": false, + "cartridge_adapter": -1 + } + }, + "cores": [ + { + "name": "default", + "id": 0, + "filename": "bitstream.rbf_r" + } + ] + } +} diff --git a/data.json b/data.json new file mode 100644 index 0000000..5f46ecf --- /dev/null +++ b/data.json @@ -0,0 +1,6 @@ +{ + "data": { + "magic": "APF_VER_1", + "data_slots": [] + } +} \ No newline at end of file diff --git a/input.json b/input.json new file mode 100644 index 0000000..9d615ae --- /dev/null +++ b/input.json @@ -0,0 +1,6 @@ +{ + "input": { + "magic": "APF_VER_1", + "controllers": [] + } +} \ No newline at end of file diff --git a/interact.json b/interact.json new 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z3w1tTlc9q;!mD!yUSI9=Y#Og)3wXbeH=TrwRKRQdyhHE8nP!cbq7z(>;ZCQ; zYJ6FXzlq0;)xp7n2jY{ZULY{FF?Zu0aUjM}5o$DxbCaJ=b zLhF<&lnA`yg>lQ?^6woljc+^PR#f;if@knB_|sVTUizDg%ekj!f92_8L#F<(ul7{E z_^GT|qkP8{OL`-n_}8_gy#c5GrwypRp1QBz^j)HRaO}G`zG^T1?-H0{-K&YPQeZJ=g@Bv zP^zx2@q`PZ-(lhcNg!8+La`G%XLpbea^^rmCAaH z_0;v@Yp(9ePW;c|#@CK!c6Bf6HPYP>#>0(tFPEj#O<49n|4-M;%|}{p@s5OQ`Sj)m zz9JRc%T3Zh6tXTRmVSE84JwGkO!15&x~y>#i$<=aP@R&B;v|D(jq*2^wG;=NI`|>{ zJWn0{1`7^E%E@S74> 2; + + if(bridge_wr) begin + casex(bridge_addr) + 32'hF8xx00xx: begin + case(bridge_addr[7:0]) + 8'h0: begin + host_0 <= bridge_wr_data_in; // command/status + // check for command + if(bridge_wr_data_in[31:16] == 16'h434D) begin + // host wants us to do a command + host_cmd_startval <= bridge_wr_data_in[15:0]; + host_cmd_start <= 1; + end + end + 8'h20: host_20 <= bridge_wr_data_in; // parameter data regs + 8'h24: host_24 <= bridge_wr_data_in; + 8'h28: host_28 <= bridge_wr_data_in; + 8'h2C: host_2C <= bridge_wr_data_in; + endcase + end + 32'hF8xx10xx: begin + case(bridge_addr[7:0]) + 8'h0: target_0 <= bridge_wr_data_in; // command/status + 8'h4: target_4 <= bridge_wr_data_in; // parameter data pointer + 8'h8: target_8 <= bridge_wr_data_in; // response data pointer + 8'h40: target_40 <= bridge_wr_data_in; // response data regs + 8'h44: target_44 <= bridge_wr_data_in; + 8'h48: target_48 <= bridge_wr_data_in; + 8'h4C: target_4C <= bridge_wr_data_in; + endcase + end + 32'hF8xx2xxx: begin + b_datatable_wren <= 1; + end + endcase + end + if(bridge_rd) begin + casex(bridge_addr) + 32'hF8xx00xx: begin + case(bridge_addr[7:0]) + 8'h0: bridge_rd_data_out <= host_0; // command/status + 8'h4: bridge_rd_data_out <= host_4; // parameter data pointer + 8'h8: bridge_rd_data_out <= host_8; // response data pointer + 8'h40: bridge_rd_data_out <= host_40; // response data regs + 8'h44: bridge_rd_data_out <= host_44; + 8'h48: bridge_rd_data_out <= host_48; + 8'h4C: bridge_rd_data_out <= host_4C; + endcase + end + 32'hF8xx10xx: begin + case(bridge_addr[7:0]) + 8'h0: bridge_rd_data_out <= target_0; + 8'h4: bridge_rd_data_out <= target_4; + 8'h8: bridge_rd_data_out <= target_8; + 8'h20: bridge_rd_data_out <= target_20; // parameter data regs + 8'h24: bridge_rd_data_out <= target_24; + 8'h28: bridge_rd_data_out <= target_28; + 8'h2C: bridge_rd_data_out <= target_2C; + endcase + end + 32'hF8xx2xxx: begin + bridge_rd_data_out <= b_datatable_q; + + end + endcase + end + + + + + + // host > target command executer + case(hstate) + ST_IDLE: begin + + dataslot_requestread <= 0; + dataslot_requestwrite <= 0; + savestate_start <= 0; + savestate_load <= 0; + + // there is no queueing. pocket will always make sure any outstanding host + // commands are finished before starting another + if(host_cmd_start) begin + host_cmd_start <= 0; + // save the command in case it gets clobbered later + host_cmd <= host_cmd_startval; + hstate <= ST_PARSE; + end + + end + ST_PARSE: begin + // overwrite command semaphore with busy flag + host_0 <= {16'h4255, host_cmd}; + + case(host_cmd) + 16'h0000: begin + // Request Status + host_resultcode <= 1; // default: booting + if(status_boot_done) begin + host_resultcode <= 2; // setup + if(status_setup_done) begin + host_resultcode <= 3; // idle + end else if(status_running) begin + host_resultcode <= 4; // running + end + end + hstate <= ST_DONE_CODE; + end + 16'h0010: begin + // Reset Enter + reset_n <= 0; + hstate <= ST_DONE_OK; + end + 16'h0011: begin + // Reset Exit + reset_n <= 1; + hstate <= ST_DONE_OK; + end + 16'h0080: begin + // Data slot request read + dataslot_requestread <= 1; + dataslot_requestread_id <= host_20[15:0]; + if(dataslot_requestread_ack) begin + host_resultcode <= 0; + if(!dataslot_requestread_ok) host_resultcode <= 2; + hstate <= ST_DONE_CODE; + end + end + 16'h0082: begin + // Data slot request write + dataslot_requestwrite <= 1; + dataslot_requestwrite_id <= host_20[15:0]; + if(dataslot_requestwrite_ack) begin + host_resultcode <= 0; + if(!dataslot_requestwrite_ok) host_resultcode <= 2; + hstate <= ST_DONE_CODE; + end + end + 16'h008F: begin + // Data slot access all complete + dataslot_allcomplete <= 1; + hstate <= ST_DONE_OK; + end + 16'h00A0: begin + // Savestate: Start/Query + host_40 <= savestate_supported; + host_44 <= savestate_addr; + host_48 <= savestate_size; + + host_resultcode <= 0; + if(savestate_start_busy) host_resultcode <= 1; + if(savestate_start_ok) host_resultcode <= 2; + if(savestate_start_err) host_resultcode <= 3; + + if(host_20[0]) begin + // Request Start! + savestate_start <= 1; + // stay in this state until ack'd + if(savestate_start_ack) begin + hstate <= ST_DONE_CODE; + end + end else begin + hstate <= ST_DONE_CODE; + end + end + 16'h00A4: begin + // Savestate: Load/Query + host_40 <= savestate_supported; + host_44 <= savestate_addr; + host_48 <= savestate_maxloadsize; + + host_resultcode <= 0; + if(savestate_load_busy) host_resultcode <= 1; + if(savestate_load_ok) host_resultcode <= 2; + if(savestate_load_err) host_resultcode <= 3; + + if(host_20[0]) begin + // Request Load! + savestate_load <= 1; + // stay in this state until ack'd + if(savestate_load_ack) begin + hstate <= ST_DONE_CODE; + end + end else begin + hstate <= ST_DONE_CODE; + end + end + default: begin + hstate <= ST_DONE_ERR; + end + endcase + end + ST_WORK: begin + hstate <= ST_IDLE; + end + ST_DONE_OK: begin + host_0 <= 32'h4F4B0000; // result code 0 + hstate <= ST_IDLE; + end + ST_DONE_CODE: begin + host_0 <= {16'h4F4B, host_resultcode}; + hstate <= ST_IDLE; + end + ST_DONE_ERR: begin + host_0 <= 32'h4F4BFFFF; // result code FFFF = unknown command + hstate <= ST_IDLE; + end + endcase + + + + + // target > host command executer + case(tstate) + TARG_ST_IDLE: begin + if(status_setup_done_queue) begin + status_setup_done_queue <= 0; + tstate <= TARG_ST_READYTORUN; + end + + end + TARG_ST_READYTORUN: begin + target_0 <= 32'h636D_0140; + tstate <= TARG_ST_WAITRESULT; + end + TARG_ST_WAITRESULT: begin + if(target_0[31:16] == 16'h6F6B) begin + // done + tstate <= TARG_ST_IDLE; + end + + end + endcase + + +end + + wire [31:0] b_datatable_q; + reg [9:0] b_datatable_addr; + reg b_datatable_wren; + +mf_datatable idt ( + .address_a ( datatable_addr ), + .address_b ( b_datatable_addr ), + .clock_a ( clk ), + .clock_b ( clk ), + .data_a ( datatable_data ), + .data_b ( bridge_wr_data_in ), + .wren_a ( datatable_wren ), + .wren_b ( b_datatable_wren ), + .q_a ( datatable_q ), + .q_b ( b_datatable_q ) +); + + +endmodule diff --git a/src/fpga/core/core_constraints.sdc b/src/fpga/core/core_constraints.sdc new file mode 100644 index 0000000..0319d09 --- /dev/null +++ b/src/fpga/core/core_constraints.sdc @@ -0,0 +1,14 @@ +# +# user core constraints +# +# put your clock groups in here as well as any net assignments +# + +set_clock_groups -asynchronous \ + -group { bridge_spiclk } \ + -group { clk_74a } \ + -group { clk_74b } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk } \ + -group { ic|mp1|mf_pllbase_inst|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk } diff --git a/src/fpga/core/core_top.v b/src/fpga/core/core_top.v new file mode 100644 index 0000000..35f4180 --- /dev/null +++ b/src/fpga/core/core_top.v @@ -0,0 +1,562 @@ +// +// User core top-level +// +// Instantiated by the real top-level: apf_top +// + +`default_nettype none + +module core_top ( + +// +// physical connections +// + +/////////////////////////////////////////////////// +// clock inputs 74.25mhz. not phase aligned, so treat these domains as asynchronous + +input wire clk_74a, // mainclk1 +input wire clk_74b, // mainclk1 + +/////////////////////////////////////////////////// +// cartridge interface +// switches between 3.3v and 5v mechanically +// output enable for multibit translators controlled by pic32 + +// GBA AD[15:8] +inout wire [7:0] cart_tran_bank2, +output wire cart_tran_bank2_dir, + +// GBA AD[7:0] +inout wire [7:0] cart_tran_bank3, +output wire cart_tran_bank3_dir, + +// GBA A[23:16] +inout wire [7:0] cart_tran_bank1, +output wire cart_tran_bank1_dir, + +// GBA [7] PHI# +// GBA [6] WR# +// GBA [5] RD# +// GBA [4] CS1#/CS# +// [3:0] unwired +inout wire [7:4] cart_tran_bank0, +output wire cart_tran_bank0_dir, + +// GBA CS2#/RES# +inout wire cart_tran_pin30, +output wire cart_tran_pin30_dir, +// when GBC cart is inserted, this signal when low or weak will pull GBC /RES low with a special circuit +// the goal is that when unconfigured, the FPGA weak pullups won't interfere. +// thus, if GBC cart is inserted, FPGA must drive this high in order to let the level translators +// and general IO drive this pin. +output wire cart_pin30_pwroff_reset, + +// GBA IRQ/DRQ +inout wire cart_tran_pin31, +output wire cart_tran_pin31_dir, + +// infrared +input wire port_ir_rx, +output wire port_ir_tx, +output wire port_ir_rx_disable, + +// GBA link port +inout wire port_tran_si, +output wire port_tran_si_dir, +inout wire port_tran_so, +output wire port_tran_so_dir, +inout wire port_tran_sck, +output wire port_tran_sck_dir, +inout wire port_tran_sd, +output wire port_tran_sd_dir, + +/////////////////////////////////////////////////// +// cellular psram 0 and 1, two chips (64mbit x2 dual die per chip) + +output wire [21:16] cram0_a, +inout wire [15:0] cram0_dq, +input wire cram0_wait, +output wire cram0_clk, +output wire cram0_adv_n, +output wire cram0_cre, +output wire cram0_ce0_n, +output wire cram0_ce1_n, +output wire cram0_oe_n, +output wire cram0_we_n, +output wire cram0_ub_n, +output wire cram0_lb_n, + +output wire [21:16] cram1_a, +inout wire [15:0] cram1_dq, +input wire cram1_wait, +output wire cram1_clk, +output wire cram1_adv_n, +output wire cram1_cre, +output wire cram1_ce0_n, +output wire cram1_ce1_n, +output wire cram1_oe_n, +output wire cram1_we_n, +output wire cram1_ub_n, +output wire cram1_lb_n, + +/////////////////////////////////////////////////// +// sdram, 512mbit 16bit + +output wire [12:0] dram_a, +output wire [1:0] dram_ba, +inout wire [15:0] dram_dq, +output wire [1:0] dram_dqm, +output wire dram_clk, +output wire dram_cke, +output wire dram_ras_n, +output wire dram_cas_n, +output wire dram_we_n, + +/////////////////////////////////////////////////// +// sram, 1mbit 16bit + +output wire [16:0] sram_a, +inout wire [15:0] sram_dq, +output wire sram_oe_n, +output wire sram_we_n, +output wire sram_ub_n, +output wire sram_lb_n, + +/////////////////////////////////////////////////// +// vblank driven by dock for sync in a certain mode + +input wire vblank, + +/////////////////////////////////////////////////// +// i/o to 6515D breakout usb uart + +output wire dbg_tx, +input wire dbg_rx, + +/////////////////////////////////////////////////// +// i/o pads near jtag connector user can solder to + +output wire user1, +input wire user2, + +/////////////////////////////////////////////////// +// RFU internal i2c bus + +inout wire aux_sda, +output wire aux_scl, + +/////////////////////////////////////////////////// +// RFU, do not use +output wire vpll_feed, + + +// +// logical connections +// + +/////////////////////////////////////////////////// +// video, audio output to scaler +output wire [23:0] video_rgb, +output wire video_rgb_clock, +output wire video_rgb_clock_90, +output wire video_de, +output wire video_skip, +output wire video_vs, +output wire video_hs, + +output wire audio_mclk, +input wire audio_adc, +output wire audio_dac, +output wire audio_lrck, + +/////////////////////////////////////////////////// +// bridge bus connection +// synchronous to clk_74a +output wire bridge_endian_little, +input wire [31:0] bridge_addr, +input wire bridge_rd, +output reg [31:0] bridge_rd_data, +input wire bridge_wr, +input wire [31:0] bridge_wr_data, + +/////////////////////////////////////////////////// +// controller data +// +// key bitmap: +// [0] dpad_up +// [1] dpad_down +// [2] dpad_left +// [3] dpad_right +// [4] face_a +// [5] face_b +// [6] face_x +// [7] face_y +// [8] trig_l1 +// [9] trig_r1 +// [10] trig_l2 +// [11] trig_r2 +// [12] trig_l3 +// [13] trig_r3 +// [14] face_select +// [15] face_start +// joy values - unsigned +// [ 7: 0] lstick_x +// [15: 8] lstick_y +// [23:16] rstick_x +// [31:24] rstick_y +// trigger values - unsigned +// [ 7: 0] ltrig +// [15: 8] rtrig +// +input wire [15:0] cont1_key, +input wire [15:0] cont2_key, +input wire [15:0] cont3_key, +input wire [15:0] cont4_key, +input wire [31:0] cont1_joy, +input wire [31:0] cont2_joy, +input wire [31:0] cont3_joy, +input wire [31:0] cont4_joy, +input wire [15:0] cont1_trig, +input wire [15:0] cont2_trig, +input wire [15:0] cont3_trig, +input wire [15:0] cont4_trig + +); + +// not using the IR port, so turn off both the LED, and +// disable the receive circuit to save power +assign port_ir_tx = 0; +assign port_ir_rx_disable = 1; + +// bridge endianness +assign bridge_endian_little = 0; + +// cart is unused, so set all level translators accordingly +// directions are 0:IN, 1:OUT +assign cart_tran_bank3 = 8'hzz; +assign cart_tran_bank3_dir = 1'b0; +assign cart_tran_bank2 = 8'hzz; +assign cart_tran_bank2_dir = 1'b0; +assign cart_tran_bank1 = 8'hzz; +assign cart_tran_bank1_dir = 1'b0; +assign cart_tran_bank0 = 4'hf; +assign cart_tran_bank0_dir = 1'b1; +assign cart_tran_pin30 = 1'b0; // reset or cs2, we let the hw control it by itself +assign cart_tran_pin30_dir = 1'bz; +assign cart_pin30_pwroff_reset = 1'b0; // hardware can control this +assign cart_tran_pin31 = 1'bz; // input +assign cart_tran_pin31_dir = 1'b0; // input + +// link port is input only +assign port_tran_so = 1'bz; +assign port_tran_so_dir = 1'b0; // SO is output only +assign port_tran_si = 1'bz; +assign port_tran_si_dir = 1'b0; // SI is input only +assign port_tran_sck = 1'bz; +assign port_tran_sck_dir = 1'b0; // clock direction can change +assign port_tran_sd = 1'bz; +assign port_tran_sd_dir = 1'b0; // SD is input and not used + + +// for bridge write data, we just broadcast it to all bus devices +// for bridge read data, we have to mux it +// add your own devices here +always @(*) begin + casex(bridge_addr) + 32'h10xxxxxx: begin + // example + // bridge_rd_data <= example_device_data; + end + 32'hF8xxxxxx: begin + bridge_rd_data <= cmd_bridge_rd_data; + end + endcase +end + + +// +// host/target command handler +// + wire reset_n; // driven by host commands, can be used as core-wide reset + wire [31:0] cmd_bridge_rd_data; + +// bridge host commands +// synchronous to clk_74a + wire status_boot_done = pll_core_locked; + wire status_setup_done = pll_core_locked; // rising edge triggers a target command + wire status_running = reset_n; // we are running as soon as reset_n goes high + + wire dataslot_requestread; + wire [15:0] dataslot_requestread_id; + wire dataslot_requestread_ack = 1; + wire dataslot_requestread_ok = 1; + + wire dataslot_requestwrite; + wire [15:0] dataslot_requestwrite_id; + wire dataslot_requestwrite_ack = 1; + wire dataslot_requestwrite_ok = 1; + + wire dataslot_allcomplete; + + wire savestate_supported; + wire [31:0] savestate_addr; + wire [31:0] savestate_size; + wire [31:0] savestate_maxloadsize; + + wire savestate_start; + wire savestate_start_ack; + wire savestate_start_busy; + wire savestate_start_ok; + wire savestate_start_err; + + wire savestate_load; + wire savestate_load_ack; + wire savestate_load_busy; + wire savestate_load_ok; + wire savestate_load_err; + +// bridge target commands +// synchronous to clk_74a + + +// bridge data slot access + + wire [9:0] datatable_addr; + wire datatable_wren; + wire [31:0] datatable_data; + wire [31:0] datatable_q; + +core_bridge_cmd icb ( + + .clk ( clk_74a ), + .reset_n ( reset_n ), + + .bridge_endian_little ( bridge_endian_little ), + .bridge_addr ( bridge_addr ), + .bridge_rd ( bridge_rd ), + .bridge_rd_data ( cmd_bridge_rd_data ), + .bridge_wr ( bridge_wr ), + .bridge_wr_data ( bridge_wr_data ), + + .status_boot_done ( status_boot_done ), + .status_setup_done ( status_setup_done ), + .status_running ( status_running ), + + .dataslot_requestread ( dataslot_requestread ), + .dataslot_requestread_id ( dataslot_requestread_id ), + .dataslot_requestread_ack ( dataslot_requestread_ack ), + .dataslot_requestread_ok ( dataslot_requestread_ok ), + + .dataslot_requestwrite ( dataslot_requestwrite ), + .dataslot_requestwrite_id ( dataslot_requestwrite_id ), + .dataslot_requestwrite_ack ( dataslot_requestwrite_ack ), + .dataslot_requestwrite_ok ( dataslot_requestwrite_ok ), + + .dataslot_allcomplete ( dataslot_allcomplete ), + + .savestate_supported ( savestate_supported ), + .savestate_addr ( savestate_addr ), + .savestate_size ( savestate_size ), + .savestate_maxloadsize ( savestate_maxloadsize ), + + .savestate_start ( savestate_start ), + .savestate_start_ack ( savestate_start_ack ), + .savestate_start_busy ( savestate_start_busy ), + .savestate_start_ok ( savestate_start_ok ), + .savestate_start_err ( savestate_start_err ), + + .savestate_load ( savestate_load ), + .savestate_load_ack ( savestate_load_ack ), + .savestate_load_busy ( savestate_load_busy ), + .savestate_load_ok ( savestate_load_ok ), + .savestate_load_err ( savestate_load_err ), + + .datatable_addr ( datatable_addr ), + .datatable_wren ( datatable_wren ), + .datatable_data ( datatable_data ), + .datatable_q ( datatable_q ), + +); + + + +//////////////////////////////////////////////////////////////////////////////////////// + + + +// video generation +// ~12,288,000 hz pixel clock +// +// we want our video mode of 320x240 @ 60hz, this results in 204800 clocks per frame +// we need to add hblank and vblank times to this, so there will be a nondisplay area. +// it can be thought of as a border around the visible area. +// to make numbers simple, we can have 400 total clocks per line, and 320 visible. +// dividing 204800 by 400 results in 512 total lines per frame, and 240 visible. +// this pixel clock is fairly high for the relatively low resolution, but that's fine. +// PLL output has a minimum output frequency anyway. + + +assign video_rgb_clock = clk_core_12288; +assign video_rgb_clock_90 = clk_core_12288_90deg; +assign video_rgb = vidout_rgb; +assign video_de = vidout_de; +assign video_skip = vidout_skip; +assign video_vs = vidout_vs; +assign video_hs = vidout_hs; + + localparam VID_V_BPORCH = 'd10; + localparam VID_V_ACTIVE = 'd240; + localparam VID_V_TOTAL = 'd512; + localparam VID_H_BPORCH = 'd10; + localparam VID_H_ACTIVE = 'd320; + localparam VID_H_TOTAL = 'd400; + + reg [15:0] frame_count; + + reg [9:0] x_count; + reg [9:0] y_count; + + wire [9:0] visible_x = x_count - VID_H_BPORCH; + wire [9:0] visible_y = y_count - VID_V_BPORCH; + + reg [23:0] vidout_rgb; + reg vidout_de, vidout_de_1; + reg vidout_skip; + reg vidout_vs; + reg vidout_hs, vidout_hs_1; + + reg [9:0] square_x = 'd135; + reg [9:0] square_y = 'd95; + +always @(posedge clk_core_12288 or negedge reset_n) begin + + if(~reset_n) begin + + x_count <= 0; + y_count <= 0; + + end else begin + vidout_de <= 0; + vidout_skip <= 0; + vidout_vs <= 0; + vidout_hs <= 0; + + vidout_hs_1 <= vidout_hs; + vidout_de_1 <= vidout_de; + + // x and y counters + x_count <= x_count + 1'b1; + if(x_count == VID_H_TOTAL-1) begin + x_count <= 0; + + y_count <= y_count + 1'b1; + if(y_count == VID_V_TOTAL-1) begin + y_count <= 0; + end + end + + // generate sync + if(x_count == 0 && y_count == 0) begin + // sync signal in back porch + // new frame + vidout_vs <= 1; + frame_count <= frame_count + 1'b1; + end + + // we want HS to occur a bit after VS, not on the same cycle + if(x_count == 3) begin + // sync signal in back porch + // new line + vidout_hs <= 1; + end + + // inactive screen areas are black + vidout_rgb <= 24'h0; + // generate active video + if(x_count >= VID_H_BPORCH && x_count < VID_H_ACTIVE+VID_H_BPORCH) begin + + if(y_count >= VID_V_BPORCH && y_count < VID_V_ACTIVE+VID_V_BPORCH) begin + // data enable. this is the active region of the line + vidout_de <= 1; + + vidout_rgb[23:16] <= 8'd60; + vidout_rgb[15:8] <= 8'd60; + vidout_rgb[7:0] <= 8'd60; + + end + end + end +end + + + + +// +// audio i2s silence generator +// see other examples for actual audio generation +// + +assign audio_mclk = audgen_mclk; +assign audio_dac = audgen_dac; +assign audio_lrck = audgen_lrck; + +// generate MCLK = 12.288mhz with fractional accumulator + reg [21:0] audgen_accum; + reg audgen_mclk; + parameter [20:0] CYCLE_48KHZ = 21'd122880 * 2; +always @(posedge clk_74a) begin + audgen_accum <= audgen_accum + CYCLE_48KHZ; + if(audgen_accum >= 21'd742500) begin + audgen_mclk <= ~audgen_mclk; + audgen_accum <= audgen_accum - 21'd742500 + CYCLE_48KHZ; + end +end + +// generate SCLK = 3.072mhz by dividing MCLK by 4 + reg [1:0] aud_mclk_divider; + wire audgen_sclk = aud_mclk_divider[1] /* synthesis keep*/; + reg audgen_lrck_1; +always @(posedge audgen_mclk) begin + aud_mclk_divider <= aud_mclk_divider + 1'b1; +end + +// shift out audio data as I2S +// 32 total bits per channel, but only 16 active bits at the start and then 16 dummy bits +// + reg [4:0] audgen_lrck_cnt; + reg audgen_lrck; + reg audgen_dac; +always @(negedge audgen_sclk) begin + audgen_dac <= 1'b0; + // 48khz * 64 + audgen_lrck_cnt <= audgen_lrck_cnt + 1'b1; + if(audgen_lrck_cnt == 31) begin + // switch channels + audgen_lrck <= ~audgen_lrck; + + end +end + + +/////////////////////////////////////////////// + + + wire clk_core_12288; + wire clk_core_12288_90deg; + + wire pll_core_locked; + +mf_pllbase mp1 ( + .refclk ( clk_74a ), + .rst ( 0 ), + + .outclk_0 ( clk_core_12288 ), + .outclk_1 ( clk_core_12288_90deg ), + + .locked ( pll_core_locked ) +); + + + +endmodule diff --git a/src/fpga/core/mf_pllbase.bsf b/src/fpga/core/mf_pllbase.bsf new file mode 100644 index 0000000..b334742 --- /dev/null +++ b/src/fpga/core/mf_pllbase.bsf @@ -0,0 +1,126 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 2019 Intel Corporation. All rights reserved. +Your use of Intel Corporation's design tools, logic functions +and other software and tools, and any partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Intel Program License +Subscription Agreement, the Intel Quartus Prime License Agreement, +the Intel FPGA IP License Agreement, or other applicable license +agreement, including, without limitation, that your use is for +the sole purpose of programming logic devices manufactured by +Intel and sold by Intel or its authorized distributors. Please +refer to the applicable agreement for further details, at +https://fpgasoftware.intel.com/eula. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 0 0 160 304) + (text "mf_pllbase" (rect 48 -1 91 11)(font "Arial" (font_size 10))) + (text "inst" (rect 8 288 20 300)(font "Arial" )) + (port + (pt 0 72) + (input) + (text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8))) + (text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 48 72)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "rst" (rect 0 0 10 12)(font "Arial" (font_size 8))) + (text "rst" (rect 4 101 22 112)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 48 112)(line_width 1)) + ) + (port + (pt 160 72) + (output) + (text "outclk_0" (rect 0 0 33 12)(font "Arial" (font_size 8))) + (text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8))) + (line (pt 160 72)(pt 112 72)(line_width 1)) + ) + (port + (pt 160 112) + (output) + (text "outclk_1" (rect 0 0 31 12)(font "Arial" (font_size 8))) + (text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8))) + (line (pt 160 112)(pt 112 112)(line_width 1)) + ) + (port + (pt 160 152) + (output) + (text "outclk_2" (rect 0 0 33 12)(font "Arial" (font_size 8))) + (text "outclk_2" (rect 117 141 165 152)(font "Arial" (font_size 8))) + (line (pt 160 152)(pt 112 152)(line_width 1)) + ) + (port + (pt 160 192) + (output) + (text "outclk_3" (rect 0 0 33 12)(font "Arial" (font_size 8))) + (text "outclk_3" (rect 117 181 165 192)(font "Arial" (font_size 8))) + (line (pt 160 192)(pt 112 192)(line_width 1)) + ) + (port + (pt 160 232) + (output) + (text "outclk_4" (rect 0 0 34 12)(font "Arial" (font_size 8))) + (text "outclk_4" (rect 117 221 165 232)(font "Arial" (font_size 8))) + (line (pt 160 232)(pt 112 232)(line_width 1)) + ) + (port + (pt 160 272) + (output) + (text "locked" (rect 0 0 24 12)(font "Arial" (font_size 8))) + (text "locked" (rect 127 261 163 272)(font "Arial" (font_size 8))) + (line (pt 160 272)(pt 112 272)(line_width 1)) + ) + (drawing + (text "refclk" (rect 16 43 68 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 53 67 124 144)(font "Arial" (color 0 0 0))) + (text "reset" (rect 19 83 68 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "reset" (rect 53 107 136 224)(font "Arial" (color 0 0 0))) + (text "outclk0" (rect 113 43 268 99)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0))) + (text "outclk1" (rect 113 83 268 179)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 107 212 224)(font "Arial" (color 0 0 0))) + (text "outclk2" (rect 113 123 268 259)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 147 212 304)(font "Arial" (color 0 0 0))) + (text "outclk3" (rect 113 163 268 339)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 187 212 384)(font "Arial" (color 0 0 0))) + (text "outclk4" (rect 113 203 268 419)(font "Arial" (color 128 0 0)(font_size 9))) + (text "clk" (rect 97 227 212 464)(font "Arial" (color 0 0 0))) + (text "locked" (rect 113 243 262 499)(font "Arial" (color 128 0 0)(font_size 9))) + (text "export" (rect 82 267 200 544)(font "Arial" (color 0 0 0))) + (text " altera_pll " (rect 118 288 308 586)(font "Arial" )) + (line (pt 48 32)(pt 112 32)(line_width 1)) + (line (pt 112 32)(pt 112 288)(line_width 1)) + (line (pt 48 288)(pt 112 288)(line_width 1)) + (line (pt 48 32)(pt 48 288)(line_width 1)) + (line (pt 49 52)(pt 49 76)(line_width 1)) + (line (pt 50 52)(pt 50 76)(line_width 1)) + (line (pt 49 92)(pt 49 116)(line_width 1)) + (line (pt 50 92)(pt 50 116)(line_width 1)) + (line (pt 111 52)(pt 111 76)(line_width 1)) + (line (pt 110 52)(pt 110 76)(line_width 1)) + (line (pt 111 92)(pt 111 116)(line_width 1)) + (line (pt 110 92)(pt 110 116)(line_width 1)) + (line (pt 111 132)(pt 111 156)(line_width 1)) + (line (pt 110 132)(pt 110 156)(line_width 1)) + (line (pt 111 172)(pt 111 196)(line_width 1)) + (line (pt 110 172)(pt 110 196)(line_width 1)) + (line (pt 111 212)(pt 111 236)(line_width 1)) + (line (pt 110 212)(pt 110 236)(line_width 1)) + (line (pt 111 252)(pt 111 276)(line_width 1)) + (line (pt 110 252)(pt 110 276)(line_width 1)) + (line (pt 0 0)(pt 160 0)(line_width 1)) + (line (pt 160 0)(pt 160 304)(line_width 1)) + (line (pt 0 304)(pt 160 304)(line_width 1)) + (line (pt 0 0)(pt 0 304)(line_width 1)) + ) +) diff --git a/src/fpga/core/mf_pllbase.ppf b/src/fpga/core/mf_pllbase.ppf new file mode 100644 index 0000000..8e1d7c2 --- /dev/null +++ b/src/fpga/core/mf_pllbase.ppf @@ -0,0 +1,17 @@ + + + + + + + + + + + + + diff --git a/src/fpga/core/mf_pllbase.qip b/src/fpga/core/mf_pllbase.qip new file mode 100644 index 0000000..eed0300 --- /dev/null +++ b/src/fpga/core/mf_pllbase.qip @@ -0,0 +1,337 @@ +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "mf_pllbase" -name MISC_FILE [file join $::quartus(qip_path) "mf_pllbase.cmp"] +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_TARGETED_DEVICE_FAMILY "Cyclone V" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_GENERATED_DEVICE_FAMILY "{Cyclone V}" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_QSYS_MODE "UNKNOWN" +set_global_assignment -name SYNTHESIS_ONLY_QIP ON +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZQ==" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "mf_pllbase" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_NAME "bWZfcGxsYmFzZV8wMDAy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DISPLAY_NAME "UExMIEludGVsIEZQR0EgSVA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_REPORT_HIERARCHY "Off" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_INTERNAL "Off" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_AUTHOR "SW50ZWwgQ29ycG9yYXRpb24=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_VERSION "MTguMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_DESCRIPTION "SW50ZWwgUGhhc2UtTG9ja2VkIExvb3A=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfcHJpbnRfb3V0cHV0::ZmFsc2U=::ZGVidWdfcHJpbnRfb3V0cHV0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k::ZmFsc2U=::ZGVidWdfdXNlX3JiY190YWZfbWV0aG9k" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZGV2aWNl::NUNFQkEyRjE3QTc=::ZGV2aWNl" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9tb2Rl::RnJhY3Rpb25hbC1OIFBMTA==::UExMIE1vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==::dHJ1ZQ==::ZnJhY3Rpb25hbF92Y29fbXVsdGlwbGllcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmVyZW5jZV9jbG9ja19mcmVxdWVuY3k=::NzQuMjU=::UmVmZXJlbmNlIENsb2NrIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==::NzQuMjUgTUh6::cmVmZXJlbmNlX2Nsb2NrX2ZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2NoYW5uZWxfc3BhY2luZw==::MC4w::Q2hhbm5lbCBTcGFjaW5n" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX29wZXJhdGlvbl9tb2Rl::bm9ybWFs::T3BlcmF0aW9uIE1vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZlZWRiYWNrX2Nsb2Nr::R2xvYmFsIENsb2Nr::RmVlZGJhY2sgQ2xvY2s=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWN0aW9uYWxfY291dA==::MzI=::RnJhY3Rpb25hbCBjYXJyeSBvdXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RzbV9vdXRfc2Vs::MXN0X29yZGVy::RFNNIE9yZGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3BlcmF0aW9uX21vZGU=::bm9ybWFs::b3BlcmF0aW9uX21vZGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3VzZV9sb2NrZWQ=::dHJ1ZQ==::RW5hYmxlIGxvY2tlZCBvdXRwdXQgcG9ydA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Fkdl9wYXJhbXM=::ZmFsc2U=::RW5hYmxlIHBoeXNpY2FsIG91dHB1dCBjbG9jayBwYXJhbWV0ZXJz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX251bWJlcl9vZl9jbG9ja3M=::NQ==::TnVtYmVyIE9mIENsb2Nrcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "bnVtYmVyX29mX2Nsb2Nrcw==::NQ==::bnVtYmVyX29mX2Nsb2Nrcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX211bHRpcGx5X2ZhY3Rvcg==::MQ==::TXVsdGlwbHkgRmFjdG9yIChNLUNvdW50ZXIp" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2ZyYWNfbXVsdGlwbHlfZmFjdG9y::MQ==::RnJhY3Rpb25hbCBNdWx0aXBseSBGYWN0b3IgKEsp" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3Jfbg==::MQ==::RGl2aWRlIEZhY3RvciAoTi1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjA=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kw::MTIuMjg4::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzA=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iw::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjA=::MzI1MjAyNDM1MA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMA==::NjU=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzA=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDA=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUw::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kx::MTIuMjg4::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Ix::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE=::MzI1MjAyNDM1MA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMQ==::NjU=::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MQ==::Mjc2Ljc0MDY0MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMQ==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MQ==::MjAzNDU=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE=::OTAuMA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUx::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjI=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3ky::MTMzLjExOTk4OQ==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzI=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iy::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjI=::MzI1MjAyNDM1MA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMg==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mg==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMg==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mg==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzI=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDI=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUy::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjM=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kz::MTMzLjExOTk4OQ==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzM=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3Iz::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjM=::MzI1MjAyNDM1MA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMw==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Mw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMw==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Mw==::NTgxMQ==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzM=::LTQ1LjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDM=::MjI1LjAgZGVn::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUz::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjQ=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k0::MTMzLjExOTk4OQ==::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzQ=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I0::MTA=::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjQ=::MzI1MjAyNDM1MA==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNA==::Ng==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNA==::ZGVncmVlcw==::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NA==::NTY0Mg==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzQ=::MjcwLjA=::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDQ=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU0::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjU=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k1::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzU=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I1::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjU=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5NQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0NQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzU=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDU=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU1::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjY=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k2::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzY=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I2::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjY=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNg==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Ng==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNg==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Ng==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzY=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDY=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU2::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjc=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k3::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzc=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I3::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjc=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yNw==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5Nw==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzNw==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0Nw==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzc=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDc=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU3::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjg=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k4::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzg=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I4::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjg=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOA==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OA==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOA==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OA==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzg=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDg=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU4::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjk=::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3k5::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzk=::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3I5::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3Rvcjk=::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yOQ==::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5OQ==::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzOQ==::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0OQ==::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzk=::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDk=::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGU5::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEw::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEw::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEw::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTA=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTA=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTA=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTA=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEw::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEw::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEx::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEx::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEx::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTE=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTE=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTE=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTE=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEx::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEx::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEy::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEy::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEy::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTI=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTI=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTI=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTI=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEy::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEy::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjEz::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxMw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzEz::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxMw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjEz::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTM=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTM=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTM=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTM=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzEz::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDEz::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxMw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE0::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNA==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE0::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNA==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE0::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTQ=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTQ=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTQ=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTQ=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE0::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE0::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNA==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE1::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNQ==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE1::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNQ==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE1::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTU=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTU=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTU=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTU=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE1::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE1::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNQ==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE2::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNg==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE2::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNg==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE2::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTY=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTY=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTY=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTY=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE2::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE2::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNg==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Nhc2NhZGVfY291bnRlcjE3::ZmFsc2U=::TWFrZSB0aGlzIGEgY2FzY2FkZSBjb3VudGVy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX291dHB1dF9jbG9ja19mcmVxdWVuY3kxNw==::MTAwLjA=::RGVzaXJlZCBGcmVxdWVuY3k=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2RpdmlkZV9mYWN0b3JfYzE3::MQ==::RGl2aWRlIEZhY3RvciAoQy1Db3VudGVyKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9tdWx0aXBseV9mYWN0b3IxNw==::MQ==::QWN0dWFsIE11bHRpcGx5IEZhY3Rvcg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9mcmFjX211bHRpcGx5X2ZhY3RvcjE3::MQ==::QWN0dWFsIEZyYWN0aW9uYWwgTXVsdGlwbHkgRmFjdG9yIChLKQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9kaXZpZGVfZmFjdG9yMTc=::MQ==::QWN0dWFsIERpdmlkZSBGYWN0b3I=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9vdXRwdXRfY2xvY2tfZnJlcXVlbmN5MTc=::MCBNSHo=::QWN0dWFsIEZyZXF1ZW5jeQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BzX3VuaXRzMTc=::cHM=::UGhhc2UgU2hpZnQgdW5pdHM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0MTc=::MA==::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BoYXNlX3NoaWZ0X2RlZzE3::MC4w::UGhhc2UgU2hpZnQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2FjdHVhbF9waGFzZV9zaGlmdDE3::MA==::QWN0dWFsIFBoYXNlIFNoaWZ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2R1dHlfY3ljbGUxNw==::NTA=::RHV0eSBDeWNsZQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=::MTIuMjg3OTk5IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQw::MCBwcw==::cGhhc2Vfc2hpZnQw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTA=::NTA=::ZHV0eV9jeWNsZTA=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=::MTIuMjg3OTk5IE1Ieg==::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQx::MjAzNDUgcHM=::cGhhc2Vfc2hpZnQx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE=::NTA=::ZHV0eV9jeWNsZTE=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=::MTMzLjExOTk5MyBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQy::MCBwcw==::cGhhc2Vfc2hpZnQy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTI=::NTA=::ZHV0eV9jeWNsZTI=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=::MTMzLjExOTk5MiBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQz::NjU3MyBwcw==::cGhhc2Vfc2hpZnQz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTM=::NTA=::ZHV0eV9jeWNsZTM=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=::MTMzLjExOTk5MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ0::NTYzNCBwcw==::cGhhc2Vfc2hpZnQ0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTQ=::NTA=::ZHV0eV9jeWNsZTQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ1::MCBwcw==::cGhhc2Vfc2hpZnQ1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTU=::NTA=::ZHV0eV9jeWNsZTU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ2::MCBwcw==::cGhhc2Vfc2hpZnQ2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTY=::NTA=::ZHV0eV9jeWNsZTY=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ3::MCBwcw==::cGhhc2Vfc2hpZnQ3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTc=::NTA=::ZHV0eV9jeWNsZTc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTg=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ4::MCBwcw==::cGhhc2Vfc2hpZnQ4" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTg=::NTA=::ZHV0eV9jeWNsZTg=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTk=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQ5::MCBwcw==::cGhhc2Vfc2hpZnQ5" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTk=::NTA=::ZHV0eV9jeWNsZTk=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMA==::MCBwcw==::cGhhc2Vfc2hpZnQxMA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEw::NTA=::ZHV0eV9jeWNsZTEw" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMQ==::MCBwcw==::cGhhc2Vfc2hpZnQxMQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEx::NTA=::ZHV0eV9jeWNsZTEx" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMg==::MCBwcw==::cGhhc2Vfc2hpZnQxMg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEy::NTA=::ZHV0eV9jeWNsZTEy" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTEz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxMw==::MCBwcw==::cGhhc2Vfc2hpZnQxMw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTEz::NTA=::ZHV0eV9jeWNsZTEz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNA==::MCBwcw==::cGhhc2Vfc2hpZnQxNA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE0::NTA=::ZHV0eV9jeWNsZTE0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNQ==::MCBwcw==::cGhhc2Vfc2hpZnQxNQ==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE1::NTA=::ZHV0eV9jeWNsZTE1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNg==::MCBwcw==::cGhhc2Vfc2hpZnQxNg==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE2::NTA=::ZHV0eV9jeWNsZTE2" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3::MCBNSHo=::b3V0cHV0X2Nsb2NrX2ZyZXF1ZW5jeTE3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGhhc2Vfc2hpZnQxNw==::MCBwcw==::cGhhc2Vfc2hpZnQxNw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "ZHV0eV9jeWNsZTE3::NTA=::ZHV0eV9jeWNsZTE3" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9hdXRvX3Jlc2V0::T2Zm::UExMIEF1dG8gUmVzZXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BsbF9iYW5kd2lkdGhfcHJlc2V0::QXV0bw==::UExMIEJhbmR3aWR0aCBQcmVzZXQ=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3JlY29uZg==::ZmFsc2U=::RW5hYmxlIGR5bmFtaWMgcmVjb25maWd1cmF0aW9uIG9mIFBMTA==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX2Rwc19wb3J0cw==::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBkeW5hbWljIHBoYXNlIHNoaWZ0IHBvcnRz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuX3Bob3V0X3BvcnRz::ZmFsc2U=::RW5hYmxlIGFjY2VzcyB0byBQTEwgRFBBIG91dHB1dCBwb3J0" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3R5cGU=::R2VuZXJhbA==::UExMIFRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "cGxsX3N1YnR5cGU=::R2VuZXJhbA==::UExMIFNVQlRZUEU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl9saXN0::TS1Db3VudGVyIEhpIERpdmlkZSxNLUNvdW50ZXIgTG93IERpdmlkZSxOLUNvdW50ZXIgSGkgRGl2aWRlLE4tQ291bnRlciBMb3cgRGl2aWRlLE0tQ291bnRlciBCeXBhc3MgRW5hYmxlLE4tQ291bnRlciBCeXBhc3MgRW5hYmxlLE0tQ291bnRlciBPZGQgRGl2aWRlIEVuYWJsZSxOLUNvdW50ZXIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTAgSGkgRGl2aWRlLEMtQ291bnRlci0wIExvdyBEaXZpZGUsQy1Db3VudGVyLTAgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0wIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTAgSW5wdXQgU291cmNlLEMtQ291bnRlci0wIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTAgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTEgSGkgRGl2aWRlLEMtQ291bnRlci0xIExvdyBEaXZpZGUsQy1Db3VudGVyLTEgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0xIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTEgSW5wdXQgU291cmNlLEMtQ291bnRlci0xIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTEgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTIgSGkgRGl2aWRlLEMtQ291bnRlci0yIExvdyBEaXZpZGUsQy1Db3VudGVyLTIgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0yIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTIgSW5wdXQgU291cmNlLEMtQ291bnRlci0yIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTIgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTMgSGkgRGl2aWRlLEMtQ291bnRlci0zIExvdyBEaXZpZGUsQy1Db3VudGVyLTMgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci0zIFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTMgSW5wdXQgU291cmNlLEMtQ291bnRlci0zIEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTMgT2RkIERpdmlkZSBFbmFibGUsQy1Db3VudGVyLTQgSGkgRGl2aWRlLEMtQ291bnRlci00IExvdyBEaXZpZGUsQy1Db3VudGVyLTQgQ29hcnNlIFBoYXNlIFNoaWZ0LEMtQ291bnRlci00IFZDTyBQaGFzZSBUYXAsQy1Db3VudGVyLTQgSW5wdXQgU291cmNlLEMtQ291bnRlci00IEJ5cGFzcyBFbmFibGUsQy1Db3VudGVyLTQgT2RkIERpdmlkZSBFbmFibGUsVkNPIFBvc3QgRGl2aWRlIENvdW50ZXIgRW5hYmxlLENoYXJnZSBQdW1wIGN1cnJlbnQgKHVBKSxMb29wIEZpbHRlciBCYW5kd2lkdGggUmVzaXN0b3IgKE9obXMpICxQTEwgT3V0cHV0IFZDTyBGcmVxdWVuY3ksSy1GcmFjdGlvbmFsIERpdmlzaW9uIFZhbHVlIChEU00pLEZlZWRiYWNrIENsb2NrIFR5cGUsRmVlZGJhY2sgQ2xvY2sgTVVYIDEsRmVlZGJhY2sgQ2xvY2sgTVVYIDIsTSBDb3VudGVyIFNvdXJjZSBNVVgsUExMIEF1dG8gUmVzZXQ=::UGFyYW1ldGVyIE5hbWVz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3BhcmFtZXRlcl92YWx1ZXM=::NSw1LDI1NiwyNTYsZmFsc2UsdHJ1ZSxmYWxzZSxmYWxzZSwzMywzMiwxLDAscGhfbXV4X2NsayxmYWxzZSx0cnVlLDMzLDMyLDE3LDIscGhfbXV4X2NsayxmYWxzZSx0cnVlLDMsMywxLDAscGhfbXV4X2NsayxmYWxzZSxmYWxzZSwzLDMsNiwyLHBoX211eF9jbGssZmFsc2UsZmFsc2UsMywzLDUsNCxwaF9tdXhfY2xrLGZhbHNlLGZhbHNlLDEsMzAsMjAwMCw3OTguNzE5OTQxIE1IeiwzMjUyMDI0MzUwLGdjbGssZ2xiLGZiXzEscGhfbXV4X2NsayxmYWxzZQ==::UGFyYW1ldGVyIFZhbHVlcw==" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX21pZl9nZW5lcmF0ZQ==::ZmFsc2U=::R2VuZXJhdGUgTUlGIGZpbGU=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9taWZfZHBz::ZmFsc2U=::RW5hYmxlIER5bmFtaWMgUGhhc2UgU2hpZnQgZm9yIE1JRiBzdHJlYW1pbmc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19jbnRy::QzA=::RFBTIENvdW50ZXIgU2VsZWN0aW9u" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19udW0=::MQ==::TnVtYmVyIG9mIER5bmFtaWMgUGhhc2UgU2hpZnRz" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2Rwc19kaXI=::UG9zaXRpdmU=::RHluYW1pYyBQaGFzZSBTaGlmdCBEaXJlY3Rpb24=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX3JlZmNsa19zd2l0Y2g=::ZmFsc2U=::Q3JlYXRlIGEgc2Vjb25kIGlucHV0IGNsayAncmVmY2xrMSc=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX291dA==::ZmFsc2U=::Q3JlYXRlIGEgJ2Nhc2NhZGVfb3V0JyBzaWduYWwgdG8gY29ubmVjdCB3aXRoIGEgZG93bnN0cmVhbSBQTEw=" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_COMPONENT_PARAMETER "Z3VpX2VuYWJsZV9jYXNjYWRlX2lu::ZmFsc2U=::Q3JlYXRlIGFuIGFkanBsbGluIG9yIGNjbGsgc2lnbmFsIHRvIGNvbm5lY3Qgd2l0aCBhbiB1cHN0cmVhbSBQTEw=" + +set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase.v"] +set_global_assignment -library "mf_pllbase" -name VERILOG_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.v"] +set_global_assignment -library "mf_pllbase" -name QIP_FILE [file join $::quartus(qip_path) "mf_pllbase/mf_pllbase_0002.qip"] + +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "mf_pllbase_0002" -library "mf_pllbase" -name IP_TOOL_ENV "mwpim" diff --git a/src/fpga/core/mf_pllbase.sip b/src/fpga/core/mf_pllbase.sip new file mode 100644 index 0000000..90ac63f --- /dev/null +++ b/src/fpga/core/mf_pllbase.sip @@ -0,0 +1,6 @@ +set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_NAME "altera_pll" +set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_VERSION "18.1" +set_global_assignment -entity "mf_pllbase" -library "lib_mf_pllbase" -name IP_TOOL_ENV "mwpim" +set_global_assignment -library "lib_mf_pllbase" -name SPD_FILE [file join $::quartus(sip_path) "mf_pllbase.spd"] + +set_global_assignment -library "lib_mf_pllbase" -name MISC_FILE [file join $::quartus(sip_path) "mf_pllbase_sim/mf_pllbase.vo"] diff --git a/src/fpga/core/mf_pllbase.spd b/src/fpga/core/mf_pllbase.spd new file mode 100644 index 0000000..025504e --- /dev/null +++ b/src/fpga/core/mf_pllbase.spd @@ -0,0 +1,6 @@ + + + + + + diff --git a/src/fpga/core/mf_pllbase.v b/src/fpga/core/mf_pllbase.v new file mode 100644 index 0000000..2fa94f9 --- /dev/null +++ b/src/fpga/core/mf_pllbase.v @@ -0,0 +1,261 @@ +// megafunction wizard: %PLL Intel FPGA IP v18.1% +// GENERATION: XML +// mf_pllbase.v + +// Generated using ACDS version 18.1 646 + +`timescale 1 ps / 1 ps +module mf_pllbase ( + input wire refclk, // refclk.clk + input wire rst, // reset.reset + output wire outclk_0, // outclk0.clk + output wire outclk_1, // outclk1.clk + output wire outclk_2, // outclk2.clk + output wire outclk_3, // outclk3.clk + output wire outclk_4, // outclk4.clk + output wire locked // locked.export + ); + + mf_pllbase_0002 mf_pllbase_inst ( + .refclk (refclk), // refclk.clk + .rst (rst), // reset.reset + .outclk_0 (outclk_0), // outclk0.clk + .outclk_1 (outclk_1), // outclk1.clk + .outclk_2 (outclk_2), // outclk2.clk + .outclk_3 (outclk_3), // outclk3.clk + .outclk_4 (outclk_4), // outclk4.clk + .locked (locked) // locked.export + ); + +endmodule +// Retrieval info: +// +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval info: +// Retrieval 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b/src/fpga/core/mf_pllbase/mf_pllbase_0002.qip new file mode 100644 index 0000000..5578caa --- /dev/null +++ b/src/fpga/core/mf_pllbase/mf_pllbase_0002.qip @@ -0,0 +1,4 @@ +set_instance_assignment -name PLL_COMPENSATION_MODE NORMAL -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_CHANNEL_SPACING "0.0 KHz" -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_AUTO_RESET OFF -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" +set_instance_assignment -name PLL_BANDWIDTH_PRESET AUTO -to "*mf_pllbase_0002*|altera_pll:altera_pll_i*|*" diff --git a/src/fpga/core/mf_pllbase/mf_pllbase_0002.v b/src/fpga/core/mf_pllbase/mf_pllbase_0002.v new file mode 100644 index 0000000..4bb1a03 --- /dev/null +++ b/src/fpga/core/mf_pllbase/mf_pllbase_0002.v @@ -0,0 +1,99 @@ +`timescale 1ns/10ps +module mf_pllbase_0002( + + // interface 'refclk' + input wire refclk, + + // interface 'reset' + input wire rst, + + // interface 'outclk0' + output wire outclk_0, + + // interface 'outclk1' + output wire outclk_1, + + // interface 'outclk2' + output wire outclk_2, + + // interface 'outclk3' + output wire outclk_3, + + // interface 'outclk4' + output wire outclk_4, + + // interface 'locked' + output wire locked +); + + altera_pll #( + .fractional_vco_multiplier("true"), + .reference_clock_frequency("74.25 MHz"), + .operation_mode("normal"), + .number_of_clocks(5), + .output_clock_frequency0("12.287999 MHz"), + .phase_shift0("0 ps"), + .duty_cycle0(50), + .output_clock_frequency1("12.287999 MHz"), + .phase_shift1("20345 ps"), + .duty_cycle1(50), + .output_clock_frequency2("133.119993 MHz"), + .phase_shift2("0 ps"), + .duty_cycle2(50), + .output_clock_frequency3("133.119992 MHz"), + .phase_shift3("6573 ps"), + .duty_cycle3(50), + .output_clock_frequency4("133.119990 MHz"), + .phase_shift4("5634 ps"), + .duty_cycle4(50), + .output_clock_frequency5("0 MHz"), + .phase_shift5("0 ps"), + .duty_cycle5(50), + .output_clock_frequency6("0 MHz"), + .phase_shift6("0 ps"), + .duty_cycle6(50), + .output_clock_frequency7("0 MHz"), + .phase_shift7("0 ps"), + .duty_cycle7(50), + .output_clock_frequency8("0 MHz"), + .phase_shift8("0 ps"), + .duty_cycle8(50), + .output_clock_frequency9("0 MHz"), + .phase_shift9("0 ps"), + .duty_cycle9(50), + .output_clock_frequency10("0 MHz"), + .phase_shift10("0 ps"), + .duty_cycle10(50), + .output_clock_frequency11("0 MHz"), + .phase_shift11("0 ps"), + .duty_cycle11(50), + .output_clock_frequency12("0 MHz"), + .phase_shift12("0 ps"), + .duty_cycle12(50), + .output_clock_frequency13("0 MHz"), + .phase_shift13("0 ps"), + .duty_cycle13(50), + .output_clock_frequency14("0 MHz"), + .phase_shift14("0 ps"), + .duty_cycle14(50), + .output_clock_frequency15("0 MHz"), + .phase_shift15("0 ps"), + .duty_cycle15(50), + .output_clock_frequency16("0 MHz"), + .phase_shift16("0 ps"), + .duty_cycle16(50), + .output_clock_frequency17("0 MHz"), + .phase_shift17("0 ps"), + .duty_cycle17(50), + .pll_type("General"), + .pll_subtype("General") + ) altera_pll_i ( + .rst (rst), + .outclk ({outclk_4, outclk_3, outclk_2, outclk_1, outclk_0}), + .locked (locked), + .fboutclk ( ), + .fbclk (1'b0), + .refclk (refclk) + ); +endmodule + diff --git a/src/fpga/core/mf_pllbase_sim.f b/src/fpga/core/mf_pllbase_sim.f new file mode 100644 index 0000000..a4f4055 --- /dev/null +++ b/src/fpga/core/mf_pllbase_sim.f @@ -0,0 +1 @@ +mf_pllbase_sim/mf_pllbase.vo diff --git a/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl b/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl new file mode 100644 index 0000000..7b3d931 --- /dev/null +++ b/src/fpga/core/mf_pllbase_sim/aldec/rivierapro_setup.tcl @@ -0,0 +1,278 @@ + +# (C) 2001-2022 Altera Corporation. All rights reserved. +# Your use of Altera Corporation's design tools, logic functions and +# other software and tools, and its AMPP partner logic functions, and +# any output files any of the foregoing (including device programming +# or simulation files), and any associated documentation or information +# are expressly subject to the terms and conditions of the Altera +# Program License Subscription Agreement, Altera MegaCore Function +# License Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by Altera +# or its authorized distributors. Please refer to the applicable +# agreement for further details. + +# ACDS 18.1 646 win32 2022.06.28.14:59:52 +# ---------------------------------------- +# Auto-generated simulation script rivierapro_setup.tcl +# ---------------------------------------- +# This script provides commands to simulate the following IP detected in +# your Quartus project: +# mf_pllbase +# +# Altera recommends that you source this Quartus-generated IP simulation +# script from your own customized top-level script, and avoid editing this +# generated script. +# +# To write a top-level script that compiles Altera simulation libraries and +# the Quartus-generated IP in your project, along with your design and +# testbench files, copy the text from the TOP-LEVEL TEMPLATE section below +# into a new file, e.g. named "aldec.do", and modify the text as directed. +# +# ---------------------------------------- +# # TOP-LEVEL TEMPLATE - BEGIN +# # +# # QSYS_SIMDIR is used in the Quartus-generated IP simulation script to +# # construct paths to the files required to simulate the IP in your Quartus +# # project. By default, the IP script assumes that you are launching the +# # simulator from the IP script location. If launching from another +# # location, set QSYS_SIMDIR to the output directory you specified when you +# # generated the IP script, relative to the directory from which you launch +# # the simulator. +# # +# set QSYS_SIMDIR