Fixed workdir for ghdl in template creation

olofk · Oct 7, 2024 · fdb602a · fdb602a
1 parent 18972c4
commit fdb602a
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Showing 8 changed files with 27 additions and 13 deletions.
diff --git a/README.rst b/README.rst
@@ -136,7 +136,6 @@ Tada! We have simulated. As an exercise, try to just change the tool variable to
 
 Now it's time to create an FPGA image instead
 
-
 As you have seen, Edalize is an award-winning tool for interfacing EDA tools, so
 
 **Edalize it, don't criticize it!**

diff --git a/edalize/ghdl.py b/edalize/ghdl.py
@@ -96,6 +96,7 @@ def configure_main(self):
 
         libraries = collections.OrderedDict()
         library_options = "--work={lib} --workdir=./{lib}"
+        top_workdir_options = "--workdir=./{lib}"
         ghdlimport = ""
         vhdl_sources = ""
 
@@ -114,6 +115,11 @@ def configure_main(self):
             libraries[top[0]] = []
             top_libraries = library_options.format(lib=top[0])
 
+        top_workdir = ""
+        if len(top) > 1:
+            libraries[top[0]] = []
+            top_workdir = top_workdir_options.format(lib=top[0])
+
         top_unit = top[-1]
 
         for f in src_files:
@@ -154,7 +160,7 @@ def configure_main(self):
                 "run_options": " ".join(run_options),
                 "make_libraries_directories": make_libraries_directories,
                 "ghdlimport": ghdlimport,
-                "top_libraries": top_libraries,
+                "top_workdir": top_workdir,
             },
         )
 

diff --git a/edalize/templates/ghdl/Makefile.j2 b/edalize/templates/ghdl/Makefile.j2
@@ -4,7 +4,7 @@ TOPLEVEL = {{ toplevel }}
 TOPLEVEL_LIBS = {{ top_libraries }}
 ANALYZE_OPTIONS = {{ analyze_options }}
 RUN_OPTIONS = {{ run_options }}
-
+TOP_WORKDIR = {{ top_workdir }}
 VHDL_SOURCES = {{ vhdl_sources }}
 
 all: work-obj{{ standard }}.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
 	$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
 
 $(TOPLEVEL): $(VHDL_SOURCES) work-obj{{ standard }}.cf
-	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
+	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
 
 $(TOPLEVEL).v: $(VHDL_SOURCES) work-obj{{ standard }}.cf
 	$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

diff --git a/tests/edalize_common.py b/tests/edalize_common.py
@@ -4,9 +4,12 @@
 import shutil
 
 import pytest
+import logging
 
 from edalize.edatool import get_edatool
 
+logger = logging.getLogger('Edalize')
+logger.setLevel (logging.INFO)
 
 tests_dir = os.path.dirname(__file__)
 
@@ -136,9 +139,15 @@ def compare_files(ref_dir, work_root, files):
         if "GOLDEN_RUN" in os.environ:
             shutil.copy(generated_file, reference_file)
 
+
         with open(reference_file) as fref, open(generated_file) as fgen:
-            assert fref.read() == fgen.read(), f
+            if fref.read() != fgen.read():
+                logger.info(f"{fref}")
+                logger.info(f"{fgen}")
+
 
+        with open(reference_file) as fref, open(generated_file) as fgen:
+            assert fref.read() == fgen.read(), f
 
 def get_flow(name):
     return getattr(import_module("edalize.flows.{}".format(name)), name.capitalize())

diff --git a/tests/test_ghdl/test01/Makefile b/tests/test_ghdl/test01/Makefile
@@ -4,7 +4,7 @@ TOPLEVEL = top_module
 TOPLEVEL_LIBS = 
 ANALYZE_OPTIONS = some analyze_options -P./libx
 RUN_OPTIONS = a few run_options
-
+TOP_WORKDIR = 
 VHDL_SOURCES =  vhdl_file.vhd vhdl_lfile vhdl2008_file
 
 all: work-obj08.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
 	$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
 
 $(TOPLEVEL): $(VHDL_SOURCES) work-obj08.cf
-	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
+	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
 
 $(TOPLEVEL).v: $(VHDL_SOURCES) work-obj08.cf
 	$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

diff --git a/tests/test_ghdl/test02/Makefile b/tests/test_ghdl/test02/Makefile
@@ -4,7 +4,7 @@ TOPLEVEL = top_module
 TOPLEVEL_LIBS = 
 ANALYZE_OPTIONS = some analyze_options -P./libx
 RUN_OPTIONS = a few run_options
-
+TOP_WORKDIR = 
 VHDL_SOURCES =  vhdl_file.vhd vhdl_lfile
 
 all: work-obj93.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
 	$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
 
 $(TOPLEVEL): $(VHDL_SOURCES) work-obj93.cf
-	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
+	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
 
 $(TOPLEVEL).v: $(VHDL_SOURCES) work-obj93.cf
 	$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

diff --git a/tests/test_ghdl/test03/Makefile b/tests/test_ghdl/test03/Makefile
@@ -4,7 +4,7 @@ TOPLEVEL = top_module
 TOPLEVEL_LIBS = 
 ANALYZE_OPTIONS = --ieee=synopsys -P./libx
 RUN_OPTIONS = a few run_options
-
+TOP_WORKDIR = 
 VHDL_SOURCES =  vhdl_file.vhd vhdl_lfile
 
 all: work-obj08.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
 	$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
 
 $(TOPLEVEL): $(VHDL_SOURCES) work-obj08.cf
-	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
+	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
 
 $(TOPLEVEL).v: $(VHDL_SOURCES) work-obj08.cf
 	$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)

diff --git a/tests/test_ghdl/test04/Makefile b/tests/test_ghdl/test04/Makefile
@@ -4,7 +4,7 @@ TOPLEVEL = vhdl_lfile
 TOPLEVEL_LIBS = --work=libx --workdir=./libx
 ANALYZE_OPTIONS = some analyze_options -P./libx
 RUN_OPTIONS = a few run_options
-
+TOP_WORKDIR = --workdir=./libx
 VHDL_SOURCES =  vhdl_file.vhd vhdl_lfile vhdl2008_file
 
 all: work-obj08.cf
@@ -13,7 +13,7 @@ run: $(TOPLEVEL)
 	$(EDALIZE_LAUNCHER) ghdl -r $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL) $(RUN_OPTIONS) $(EXTRA_OPTIONS)
 
 $(TOPLEVEL): $(VHDL_SOURCES) work-obj08.cf
-	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)
+	$(EDALIZE_LAUNCHER) ghdl -m $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOP_WORKDIR) $(TOPLEVEL)
 
 $(TOPLEVEL).v: $(VHDL_SOURCES) work-obj08.cf
 	$(EDALIZE_LAUNCHER) ghdl --synth --out=verilog $(STD) $(ANALYZE_OPTIONS) $(TOPLEVEL_LIBS) $(TOPLEVEL)