Husky: frequency-dependent ADC sampling clock phase when using external clock

[jpcrypt]

When scope.clock.clkgen_src = 'extclk', the relative phase between the HS1 target clock and the ADC sampling clock depends on the target clock frequency.

This is similar, but not directly related to #490: with that issue fixed, a frequency-dependent phase is still observed. The phase observed with this present issue is 100% reproducible: for a given target clock frequency, the ADC sampling phase will always be the same (if a fix to #490 has been applied). The ADC clock rising edge can be anywhere within the target clock period.

This issue is due to not using the CDCI6214 PLL's zero-delay mode and has been resolved with help from TI; a fix is forthcoming as part of other fixes and improvements to the Husky clock management code.

For users currently using the CW develop branch or the 5.7.0 release, this, in addition to related clock phase issues (#490, #499) means that if you're using scope.clock.clkgen_src = 'extclk', the ADC sampling phase:

1. may not be consistent from run to run
2. will vary if you change the target clock.

[jpcrypt]

A consequence of this fix: zero-delay mode can't be used when the reference (target) clock is > 100 MHz.
In that case, we can't make any promises on the phase relationship between the target and ADC clocks, or define what that phase is. However, our tests show that this phase is constant, but frequency-dependent.