diff --git a/Makefile b/Makefile index 1a9f8ae..f6dc5c6 100644 --- a/Makefile +++ b/Makefile @@ -4,11 +4,11 @@ RUN_CMD := docker run --rm --name axi_dma \ .PHONY: run_test csr_dma.sv clean -run_test: csr_out +all: csr_out $(RUN_CMD) tox csr_out: $(RUN_CMD) rggen --plugin rggen-verilog -c config.yml -o csr_out csr_dma.xlsx clean: - @rm -rf run_dir + @rm -rf run_dir csr_out diff --git a/rggen-verilog-rtl b/rggen-verilog-rtl index ad2de87..87e31da 160000 --- a/rggen-verilog-rtl +++ b/rggen-verilog-rtl @@ -1 +1 @@ -Subproject commit ad2de875b474810da995a47d947469a740384f01 +Subproject commit 87e31da5397f4ed5cfcb282a4112124b88cd4ee5 diff --git a/rtl/axi_dma_wrapper.sv b/rtl/axi_dma_wrapper.sv index 432d4c4..949cb10 100644 --- a/rtl/axi_dma_wrapper.sv +++ b/rtl/axi_dma_wrapper.sv @@ -12,50 +12,47 @@ module axi_dma_wrapper input rst, // CSR DMA I/F input s_axil_mosi_t dma_csr_mosi_i, - output s_axil_mosi_t dma_csr_miso_o, + output s_axil_miso_t dma_csr_miso_o, // Master DMA I/F output s_axi_mosi_t dma_m_mosi_o, - input s_axi_mosi_t dma_m_miso_i, + input s_axi_miso_t dma_m_miso_i, // Triggers - IRQs output logic dma_done_o, output logic dma_error_o ); - rggen_axi4lite_if.slave csr_axi_if; - always_comb begin dma_m_mosi_o = s_axi_mosi_t'('0); - dma_done = 1'b0; - dma_error = 1'b0; - - //csr_axi_if.awvalid = dma_csr_mosi_i.awvalid; - //dma_csr_miso_o.awready = csr_axi_if.awready; - //csr_axi_if.awid = '0; - //csr_axi_if.awaddr = dma_csr_mosi_i.awaddr; - //csr_axi_if.awprot = dma_csr_mosi_i.awprot; - //csr_axi_if.wvalid = dma_csr_mosi_i.wvalid; - //dma_csr_miso_o.wready = csr_axi_if.wready; - //csr_axi_if.wdata = dma_csr_mosi_i.wdata; - //csr_axi_if.wstrb = dma_csr_mosi_i.wstrb; - //dma_csr_miso_o.bvalid = csr_axi_if.bvalid; - //csr_axi_if.bready = dma_csr_mosi_i.bready; - //csr_axi_if.bid = '0; - //dma_csr_miso_o.bresp = csr_axi_if.bresp; - //csr_axi_if.arvalid = dma_csr_mosi_i.arvalid; - //dma_csr_miso_o.arready = csr_axi_if.arready; - //csr_axi_if.arid = '0; - //csr_axi_if.araddr = dma_csr_mosi_i.araddr; - //csr_axi_if.arprot = dma_csr_mosi_i.arprot; - //dma_csr_miso_o.rvalid = csr_axi_if.rvalid; - //csr_axi_if.rready = dma_csr_mosi_i.rready; - //csr_axi_if.rid = '0; - //dma_csr_miso_o.rresp = csr_axi_if.rresp; - //dma_csr_miso_o.rdata = csr_axi_if.rdata; + dma_done_o = 1'b0; + dma_error_o = 1'b0; end + /* verilator lint_off WIDTH */ csr_dma u_csr_dma( .i_clk (clk), .i_rst_n (~rst), - .axi4lite_if (csr_axi_if), + .i_awvalid (dma_csr_mosi_i.awvalid), + .o_awready (dma_csr_miso_o.awready), + .i_awid ('0), + .i_awaddr (dma_csr_mosi_i.awaddr), + .i_awprot (dma_csr_mosi_i.awprot), + .i_wvalid (dma_csr_mosi_i.wvalid), + .o_wready (dma_csr_miso_o.wready), + .i_wdata (dma_csr_mosi_i.wdata), + .i_wstrb (dma_csr_mosi_i.wstrb), + .o_bvalid (dma_csr_miso_o.bvalid), + .i_bready (dma_csr_mosi_i.bready), + .o_bid (), + .o_bresp (dma_csr_miso_o.bresp), + .i_arvalid (dma_csr_mosi_i.arvalid), + .o_arready (dma_csr_miso_o.arready), + .i_arid (), + .i_araddr (dma_csr_mosi_i.araddr), + .i_arprot (dma_csr_mosi_i.arprot), + .o_rvalid (dma_csr_miso_o.rvalid), + .i_rready (dma_csr_mosi_i.rready), + .o_rid (), + .o_rdata (dma_csr_miso_o.rdata), + .o_rresp (dma_csr_miso_o.rresp), .o_dma_control_go (), .o_dma_control_abort (), .i_dma_status_done ('0), @@ -70,5 +67,6 @@ module axi_dma_wrapper .o_dma_descriptor_read_mode (), .o_dma_descriptor_enable () ); + /* verilator lint_on WIDTH */ endmodule diff --git a/rtl/verilator_config.vlt b/rtl/verilator_config.vlt new file mode 100644 index 0000000..64423c3 --- /dev/null +++ b/rtl/verilator_config.vlt @@ -0,0 +1,4 @@ +`verilator_config +lint_off -rule WIDTH -file "**/rggen_register_common.v" +lint_off -rule WIDTH -file "**/rggen_adapter_common.v" +lint_off -rule UNSIGNED -file "**/rggen_address_decoder.v" diff --git a/tb/common/constants.py b/tb/common/constants.py index 5801170..3b0f9ca 100644 --- a/tb/common/constants.py +++ b/tb/common/constants.py @@ -21,13 +21,16 @@ class cfg_const: TESTS_DIR = os.path.dirname(os.path.abspath(__file__)) RTL_DIR = os.path.join(TESTS_DIR,"../../rtl/") RGGEN_V_DIR = os.path.join(TESTS_DIR,"../../rggen-verilog-rtl/") + CSR_RGGEN_DIR = os.path.join(TESTS_DIR,"../../csr_out/") INC_DIR = [f'{RTL_DIR}inc',f'{RGGEN_V_DIR}'] TOPLEVEL = str(os.getenv("DUT")) SIMULATOR = str(os.getenv("SIM")) VERILOG_SOURCES = [] # The sequence below is important... + VERILOG_SOURCES = ["rtl/verilator_config.vlt"] VERILOG_SOURCES = VERILOG_SOURCES + glob.glob(f'{RTL_DIR}inc/*.sv',recursive=True) VERILOG_SOURCES = VERILOG_SOURCES + glob.glob(f'{RTL_DIR}inc/*.svh',recursive=True) VERILOG_SOURCES = VERILOG_SOURCES + glob.glob(f'{RTL_DIR}**/*.sv',recursive=True) + VERILOG_SOURCES = VERILOG_SOURCES + glob.glob(f'{CSR_RGGEN_DIR}**/*.v',recursive=True) VERILOG_SOURCES = VERILOG_SOURCES + glob.glob(f'{RGGEN_V_DIR}**/*.v',recursive=True) EXTRA_ENV = {} # EXTRA_ENV['COCOTB_HDL_TIMEUNIT'] = os.getenv("TIMEUNIT") diff --git a/tb/common/testbench.py b/tb/common/testbench.py index 35c9fed..0ef2468 100644 --- a/tb/common/testbench.py +++ b/tb/common/testbench.py @@ -43,6 +43,7 @@ def __del__(self): # Need to write the last strings in the buffer in the file self.log.info("Closing log file.") self.log.removeHandler(self.file_handler) + self.file_handler.close() def set_idle_generator(self, generator=None): if generator: @@ -80,6 +81,9 @@ async def read(self, address=0x0, length=4, **kwargs): self.log.info("[AXI Master - Read] Slave = Address = ["+str(hex(address))+"] / Length = ["+str(length)+" bytes]") read = self.csr_axi_if.init_read(address=address, length=length, **kwargs) await with_timeout(read.wait(), *cfg_const.TIMEOUT_AXI) + # try: + # except SimTimeoutError: + # print("[Error] AXI 4 read timeout") resp = read.data # read.data => AxiReadResp return resp diff --git a/tb/test_dma_basic.py b/tb/test_dma_basic.py index 9f4ce4c..f3b4467 100644 --- a/tb/test_dma_basic.py +++ b/tb/test_dma_basic.py @@ -34,20 +34,17 @@ async def run_test(dut, config_clk="100MHz", idle_inserter=None, backpressure_in # tb.set_backpressure_generator(backpressure_inserter) await tb.setup_clks(config_clk) await tb.rst(config_clk) - rand_data = bytearray(tb._get_random_string(length=4),'utf-8') - try: - req = await tb.write(address=0x30, data=rand_data) - except SimTimeoutError: - print("AXI 4 Lite TIMEOUT!!!!!!!!!!!") + resp_row = await tb.read(address=0x04, length=4) + assert resp_row.resp == AxiResp.OKAY, "AXI bus should not have raised an error here!" def cycle_pause(): return itertools.cycle([1, 1, 1, 0]) if cocotb.SIM_NAME: factory = TestFactory(test_function=run_test) - factory.add_option("config_clk", ["100MHz", "200MHz"]) - factory.add_option("idle_inserter", [None, cycle_pause]) - factory.add_option("backpressure_inserter", [None, cycle_pause]) + # factory.add_option("config_clk", ["100MHz", "200MHz"]) + # factory.add_option("idle_inserter", [None, cycle_pause]) + # factory.add_option("backpressure_inserter", [None, cycle_pause]) factory.generate_tests() @pytest.mark.parametrize("flavor",cfg_const.regression_setup) @@ -75,6 +72,7 @@ def test_dma_basic(flavor): toplevel=cfg_const.TOPLEVEL, module=module, sim_build=SIM_BUILD, + # compile_args=["-f verilator.flags"], extra_env=cfg_const.EXTRA_ENV, extra_args=extra_args_sim )