From 34555cfef1239be2b52e046021e0fbfbe4d79633 Mon Sep 17 00:00:00 2001 From: Anderson Ignacio Date: Sun, 16 Oct 2022 17:56:34 +0100 Subject: [PATCH] Added parameters to shrink the design size Signed-off-by: Anderson Ignacio --- csr_dma.xlsx | Bin 12120 -> 12109 bytes csr_out/csr_dma.h | 60 ++++++++++++++++---------------- csr_out/csr_dma.md | 40 ++++++++-------------- csr_out/csr_dma.sv | 36 ++++++++++---------- csr_out/csr_dma.v | 68 ++++++++++++++++++------------------- csr_out/csr_dma_ral_pkg.sv | 32 ++++++----------- rtl/dma_streamer.sv | 37 ++++++++++++-------- rtl/inc/dma_pkg.svh | 30 +++++++++++----- tb/common/constants.py | 18 +++++++--- tb/common/testbench.py | 6 ++-- tb/test_dma_error.py | 4 ++- tb/test_dma_unaligned.py | 4 ++- tox.ini | 2 +- 13 files changed, 173 insertions(+), 164 deletions(-) diff --git a/csr_dma.xlsx b/csr_dma.xlsx index fd0ac42e62605b62bc74cccb70dc3710efdc7e55..a7dfd65e76c07742f21ac43acf7d2a0f8bbf0274 100644 GIT binary patch delta 5576 zcmZ8lWmFVgyB&}aB!(0LK|)HpTM1F(}s82Y~7 zd%wE({5fl#z4zIFp7qqU{(yc3J`N6^Lq*35IsmW+BgbKd7N?-;Q5y&wz>tF$neHxe54f2S%nBQM{Bl< zDAA-UOI;%$dhlv}j?AcLh9P*B8ZTpuJ)cN8Dx-SiW zo^7ue#6RG!x&ww6s1O&gMzf}T9N-D}QHa9^!nK6X1l~wR@w89>Fb{KUCc|oFW3$7Y z`|5(tq_Ys|&~uC=#=0|*6XP^7Ij{YvF@Y}ZN3(sjsc5G^`wdt5LLtb#% z$aFdel*ehLr?dPk;Yt`Qv$e+l+Auwl+!w9H2)-F0^NMNCpO4pnFIxt zpT3vK#-LH)Vh-LHimo34^w%#GH8>Thikp%_1L*R$LI*iRZ$f4xv`qAD_g5Mc6IsWV z?bBB<7?_7u#vluziGwa3?&UB&7l{ufQ_?3r)$@j{S^;8CWn6aazZZpLSAP}m<(liF z-r5QO0A98mSy&}u67A}Lb-~QNjNNpm&xYOj`yc66IddU$i9WfIq-k+xyt0@#vvZbHcy}{cR}4U2(|a ztbE)sr#yJt?%E=b>pVx;L3vAjx>?Xh;S~$h%AeUSV^2SVzVU}xypr7eRr;-R| zWSX*NGl%ObeqxaW<*1L&^Lgyvby$Gn8=b;=SKwe__L-!tI8h+{EhhmgeOw+dU<_@Mg6uq=r|MjII6$Nim~*+t;Y7Uv<%Kcu@SY)m494&F%svf1U<~IqI5N z=IjUoN1ce~R=@jpiOeo>9zyQ@;XLAM`hlAj$%XIs%8u+l5;x@U%xS1~>gsFJ zzFRuXeFA$`MCnKzgJ}0#idRC#sKDQz+StdkdPEZrmkKI5y*lct~JwRnxBc|Of z_?$FnbE}I%S#B`9RQ6V7yqx49mu{}1IaB>W=WQuxzag_4n;p2Jsj}zjd6dci_(K=* zB-AgxQgiEI+87upokYPD#G<{3hB>xq$SJ~HiU{qc)x9!Ktv7pN;hmH2hNx}``MEai z$=>{ZZR1OIIPFy5K;}Ige7bwCOH28Eqb`)x+d?8+7OsX?P7XyL8gv*@e#WvmvMeU4 zBRHfZ%}`GF@;>GP=~Hq3t`wClWRweI6gk^=6<6TE|1&(YQbu#3(=0i(;VdAkT0daz zx{mwsa1E@Xa>o3rW6EnEN?Qo+dXzM#I9)2gegwd>pO8YI5#U43}~O#BZG^@s3_5 z%2x~SHm|-G*n(h8#V)=UZHSX0zO@tXLzG&w>IPAD;JS8Jico0DGW#Fngn=g)~}}r{gA6qfT8Sgp-NDD4jp5aDGbPbaN3I zKHQ>w%Ulra$8Xx;-V`a5y+L8t2rd0}oEEfSUeF9i#`cD~=EFS}tJeYRKjnE}E>zTR z>Q@PYt6W2ABe*j~Uod-iJ$wB}^97;$vv(o5AKq5oWwMjTwYIyK_tv3`#p!W53QCl_ zRFs?x9JpUvDAk&TG7GWfR`X0Dn#AbUKwYKH5-q{U6TWjFk!$URR1+RfN9v;Q9AW$Y(iU}u zC(i(GPYmbre3z~ir_RKeXb`m=wl@zLN(#$RK)~B$pDA=;$7P-$A>G#!z}k=#xeT>+ z;}ZY7GmSYDMaTBGTZ&|^-v$|6D_87W)a17&)Fgi;PuY+yL3@{_V8GK#&QI6qUo@)K zGg9R6RN{t9TTJ3vn(Ci8$;_8R1%5>h9Yl^dN?n6)#KwgPjyFlWP2hHS$phvAl%b)} zyLhxMkGMrK+3wPE^OyPz7vEjo*1ARNyghsMzxGwoQdZt>-%W6=B=R&YA`CO5xbv^R z$lQoo3W;fTndX?3@+)3z_Plu24HVIG#_5&z)jqJEh?zdBA7z_)S^1$N03xl=5G#3$iK@7l3dBQ75-Mz8&c&QQMY;Spby6Hz}3SC${x_5MJH*x94mjvF% zx_=hBeYBihT9Gf*iMWKPVl^^{*1Njt`d@y&S6_iPfBo>QCt|% zUuW~iC6uMu*^!&W+C5d})p575)SExFf`m_MnjT~zJ4Pc@O%IH5BH!rI|9W5|s8#fA zk5qU-`omaIrDYU2jcW}_E2KObFVyW@nZ zzZG78V&gkdky?40J^@3n9L?3fJD68ToerZ_H0(ETP-eay8*UFUvZ{>|A8^KwB^NDl z-I^WaQrdQzP8Xudp{lopbf2IvzHm(V0}V+|2nQ$HRHF^7A*D2E*mHk(-!P-H zlRkq!4Zwl-_D;_FlD`kNm*OQUkx=(ANB%G&Z`u85a!IMRLfFd-UKNJMFp`iJ<0LnS zWKUYR8D*oSq)n~ELld;m?Q6f->!hszTxJ|==yX>Ml6crhTr%3O;^&J)zXGxdXRunS0%~e{V_eooa=tV zVL~)H=Sl*0T?r|idGyFn#CH&|q~oU7w@+!ihqvZJ@ut;#1s?h1gDW&AhSBX^#%bJZ z5b=&Di6~Uym-qc#N0?JHfw5`HMb6H@?9w^z&!Ho2kuN+xZ74%kra5M1-eQ)`WdFF| zWK6?@d4OP!?q{W{6B;Ui0?AVxG& z9Di&N&yL?^Y8lF1TjwaeAGx5p{(}Yd)`EBG~<2@z-@c8&w^?ZCx)0tD97Y5#wSxFkUX@YP)dZw#* z45S8B6|COSbpqY4jx?+Cnu{f(&lA$lscY8xTpnCxM*VEi zt7#B^@VfDAoSQIsa~lUOz1%sz7Yv8WM6)0P#?Q+NSuKj@D!A5o}2NM(xBU2Z(yIjH~mS~N^U>mALY{{ft{GCM(;RhKFm$(Ivs?Ub% zucGR{%NfErnk%6P&s~~pV{K~mu6jy(C1tICS~uFsn<##GL7QDau^PavEP~WcDM+Xf z;jg!I6yL_O$)P&rf*6+B4owZjBkd%Leh|iExhl{b^Zr3Soj{VzK~-6t+zS&w*nGuS zu7n;@8iaK+D)a-|(P%^VxS2@~ndF4!YTHLBRU&eJ5mMhix7k#hHUtpZnDyYL&d9Mr z+Dv!wsC7PDRc2`SFT>;+)Po;&3di-c#EEvIHg(A(hFG(G4e9yM#ni| zzDK5_hr!LY3E|>!4^Q!TH2EFcuh2lx>7nZNxL25bMWrGy4w8(WPbM)0Wycj{jPdk> zx|o6y{>b^|co$VE4mEl@vr+!&%uyi^F7h)9`Thjm`pufkW=zut9S_4JFQZb4jUR!0 z0BkouVjeoxk)%3!*90hi{x<%%{?%wbNY$0F>52@ss?s-Wm#BFK>~FH(vL0|kL4AFo z_dIW*kJd3hZjn!8guSQ27tLA*O=Fbgo7kH`?e?!2%fl~ZtcRM>XGnt8_q|I@PQvrX z45Sc;;DbVL%yB{v>y`_$o{sLFvlQcUdg%*SO#iS@e*P}tr9M+|UHpa^p8TL+gpZ%y zqQ`3jtb|=d6zPUqRc)Q8$Gz(oH1I60;epghBK-7qb~aer7|-aLnRIv`vyvf6g8KEH zY-SHOqlV=FN_0&H_kO5{JOBJfrn;s$T@f9M23vA9=rVSa;qTVTT7qK1&@iAz{qwLOR;I!{ z^_{OfKStlF>Jen-jOt7x>Em4=oQRphQ87(&#B9hIg+wf3wwKcVW2a`X2Hkc3$%cn2 zt5|aEK_q%bD>PQ3rM;{4^@Hhf;FDdi!B24D5GCD@r(J3w%cZQe-qBq&Mh#08DSWcZ z?lY^pc33SGZd;1&dlI5X5E_~&P(Vi_GamVI6ky$5mFN3u(7ia4nb6*mhr`mprcC$w zsCM^HQR=0Nxy8b4I{X;Ro?xI@v%u-cf_P%C52L+$af|~|C{_=ZfqKUc9rKry>|%qw z#5PYeo@U_ai*L5DuHP5=;~#6m%n-{F%gM`~#*&^;$d$hFt?++XF!PJ%%LFP@IUA4< zy$6%W2|_tzLL@i998^K)@h>Zl6-w2Wr~f5l z`z*so{U4`aNQVc(p2p^TkJ$%~#5>a2R(#bi3SH%@txD5Z-q8z9GsgP`eKf{b;6ucu zj<|QUtJx)mbS{F>oZCsyWGE~-^V=2w$ zpzp2NdjCNF2L6&fM`dvxOBpN&HMe5>1`yt$)1LpO_#0Rj?Z*CwGH8Fmu6}sAf{WSt zoAD&RdYy$C4XU)p4Qwj^@d&)mn62u$T3q(f|7H_n^hb zmH5noHZ9B_>q~r^4e6iq9)gi);M`d$hBZc38+sv5ekd^sp6+hGSG;bPS{L~bv_zep zymX@-IXPY}D*>Gw-y-iPNS5(o|4z_#@K`Q69sfyRXoiT2AQqwI0e`gjE>eR@?n0M8 zx59Q#UTm)$bmn~XczBs@P{Uu_2SzJS(!t@^lBvn-HuvhhALC=`-ymX?#{9Z1&Gg~x z7ry|RJ!oKTgosSBoQ!&#hhpZp+d*7;y}oew9U&pC^KuzC)Mte%KzTufKf5qJ@}~dP zCMzm2uqWA<`_ZiBvCJMMVCth^^}cu0+K&|lN9c*WrDk5Z7q3h6^`9fxTy&fur=2N7 z7{*^D-#XrL7v0DtKGl65dOse1Lsf%_T}OL;_$&+qew*Xs)jJ{fck@?W@CJnTUz^b@ zcK&}ZlDIj@(DCtLoOt9gJq{q%|DTHgD((L~-mq{EQ8Xu52ZtclzgtKy0D$6OguibW z7%As_bRk-p0WBHKfs+kwAC}6=K=pTIpaB5nPXGX-|0C#x&2UPh#lR@IM6rn2{{j6E DR=~l5 delta 5615 zcmZ8lWmFtYvK^d(puyeULx7-z2MZ*)y9_=-0zn1~9&CUR+--0TGPpaz-ICz${<3>^ z-}lbzKV7HptvdCiyX$t1n#`M2;Q)c?j`A~qkO6=_7zvOa`dtRV{XtmUc+NlC$d!;Y zAl~ULxAfW1mN3EQdtospgXfqnjnw$ct#iBMaF?DYJ$Yp)OPh3|G(38{%;3dnR%{7z zN~l);kWwe7sNg59R8xg4sTJoRdI;Ax0YG+wtXqi|^>4Wr=BZMWpf6k9bV&Uy@jIy$VKVP?2>n2ya{N0MAw z>f(@>K1vTZXUbxIcHw)Q4fppDX%nnCL~mv_@yXpuHzsDAOE?`=~o^Y+1;&w9XU3uvDNq^kUqOOc`FDgdcP*EqFXI%CFey zrZZ9Gw@Z;<(GL4yTgvw}=xx$3)k$BwtIl7PpA7)oxg~j_#Ou8S{quE-{U6&%(K|Re zj?fHYju?h@KAc@VUDwKFCs2yDPIjpQiZN8{+Z?7MiaKGq0Kw)0XP2}%8EfEcg$P^b zOtI=dXfRU^i;{RaGKLt?bB&Ix3-8rCihA*Z$qCshv?J0A7po<2J}k=QEW6g+Zp+=< z#+-8m_|4s>B!6=}>&BvB!+6=yEqZP!XsV*th$^57>^IJ(t766nDypwcI$nq!kD)juAGq#Q4YHKua{|@oE<5111xx2-v{X z?IbtP11%{v2hhiSPVDtCGr`{bI7c+<>%cKahMerHpnzkans`#VVho}cqN3y|jDg4x z3~TkRB8T37RO*Dh67e%<+qA7Vfh+!M5%#DTK6ERKIW$w!P` z>9dpNo%`>;mS2#o^u5t5TBQZ2iHrHd#UmMsJ2Y4h3K5$9lANO$jP3;k)M4o@{*(X2 zGvCe>F;9HDi5jIN=}WQn93_>#gf2*Uyd0xdhZxf~pO;g5)ri$0qOUExF$CnDUM&?5FfF;Op-Sg}yTB$K6*lx=^ z)5iGxDMwgz##jWG5=C#Zl(j^FV4)K1ieRg=Nl+ni`G*QoOk3DQ&NYpCh}rMhT55mR zA7cVhs0?a2i*B5E85TPwk}a<0&!a=EpU!jxSlHQ`9cF!i@2#byj~d_6||hjW|GxT+eA;lQ=ns|a_T z=cp9Js8GHyPJyLgY?j}%2yOq=pv=gwryHtKOU_k`E>ohc6xa3YdU)M@plj~Fmf%BD zJz1D`JDH@p8r`-J^{>DGGx@^>GAD@?<0*W;WW8n%esP`nEqlS`&uO;DY?vXe#~FO* zIiqzNN;*rM?W`JfFYmCFM$e3vA0$p8;t|1_@p*2ILP^A{hJ;1x07BW;iyI1EKUweU zMw6>*ZubtrS8#2)t1-GbKHm|@#BOsb#i5uWuj6*5Vqi>!{`NT6n>-wQ4}11|G^Gtu zc2uqe4$oqZJ6RQ2p+>va)kt0jhhXkT#@c?$339Y_q$+ys0wq5!~C1i@!C~ z?w*``F+TZ##ucD=Ki?N5GyQ<YijL9C_!RYb7lx|4E2G#;DcgNZT&~_Usq<>u_DCptDaRe0rAZ7pn zZ~y>+mm{y6ySJmY8;_ThoooEG43{=Ff$ChoX3V#lD>SHD}s~W~%Ai-jTuyV&Fvf=)C=yzb{|c!Or1)#yqyJ zmQYIsv8!n^;UZUn(6bb1HNNPc(UcRY&*f9jla%|=<6o9+kXWSBGZ?MWHJ6ZFnm@U- zFFs73`aZxQRVXs?r~CJU#4>%ktD`blLilg_%oECN__h*MhM^UEZqAQdo|`%QK}fkU zk8+menAwMs+0gbT9`mvU21&4O)yVZtItA4Oit#&l6qBEmzHAcP{h)bGPAZk8D3{Z( zbvY<91Rf*8Ekzj|%zRPsg8~x8_MM+0l$nj$-Ppr0SJu9T<{M!gVrLpH21~6ahI93R zSv1a!B%By(rbjF}ywn(HR2hH$iu10Dh!)` zLo(bHU?vQRPRlvI&)of-xxIuk)ll$mjW%$K!4&`vlsfU9L#7KoRJx@J0!1PxN)7A3 zfRt7HPXPvX{b2mPK#YA$t2X?0anr7Au5GGxKYNa_9*T*#SmGAff`dKs%Q&5?` z(eIMaJ%pE7h&~lALgmU0K$G;cgKzJ0uXhUrze~0+(=D|b=V;DV~Rx&!2N{rGS6&M^mN9`z0#v}F%I8QT*d;w}UZkl+=;69;Vq z%NH8fFlKFjwKxTo?Q_in!8^`igH#~N9Eh@K>y~7dC=0W0ntpvO7qV2u|?T*oR z$0{F(Kgbg_OX8%9T8d>bne+Zoj?+!%ymU=>(7sM);;lR)9V4#XzelKpSVvMmjjW@X zuT{tF_dP**el!N1(~t4+1}DB2Ert$xC_@duw5tKt2^!&ncgBfBcD5>M<(OY6`)wor zL9ck01aj&3o{W|=hmp5zh%q1d-%UiGg^dn_oU))WUEun~W%1ge~X3dPut{*S8fer;ZZq95_%|2D%Cp-9hs>)(xgqAGuoC%Ioix}*r z%w{;Kw~ORVbsn{z7OqXG)!vN<0FI+Yl=zwT^WX}yD<&F*f~Mv&E`m9Y&)X>v*#CO) zY6FOnk$}o<)l5l10Du=3Ma&Nk2+(ffoYpQV-MeyiN(buo@Yj!)Xs;nGw?jhelp8U{ zV_>&`vSd@%vaAWHq$zWT&~nUGk=dGtpm>)t{|h1xclEr!soD` zVzp>hNQBC@bcPPswQK^u*a_b?4s&|Mntmqew@#-G9K5a?5gTMs-V}j;WqQe6g86DC zEa%L~)l2JvE~k!IPPUV4PuQ?p7)R|)Qe^PrsEXE=`8r%LN@hMPECF=3Fjc6PT8=$( zuc{c0Vf%Fr723@bE!7^ugf=%+yd3&AhGVpGS3M8hK{20`FsGEe zm7L^WwZUl)#&-Mtvo;tyK=SL85ft67#BkFYeDp{^?9Ecu%>xI?w$UB$9&8z_=KfyB zoA`vp>Q;}(WhfaW)l4hN{bZFvMj>9RH z*)~PV(>gMd^an?4l~ziAnm$1n3GR!E+`Bi$GlzpKyT74czO zQB&jFv_<#Ej|DZ)H;wjLc&1MeE+Uz@{j|r|EpVy5mF|^J^LEh_(Vjc?+51yhk59L! zuAjUy!x4(pE!ZHf*J07%xC)ek0%MZ0(a_t6MXHp_azcl5%*M3Xu;%^VnxCiC73th? zg5l5AKIPEQEx*6HgtfP~HA8pBJzG@f4by6cG1}G^yaTnR_f{DXvI6XGoD__QuQ39xfbHZ@qPX=Dwa}Ei&8b7Img7ZYf}YMl+V}^^(PmEjVc;OgUZI zh$a?avBZ@G6EKa2*Ft z47@L1Yp@R0z6qN5;4O%vOS;zZF%9I&+ypdCe!bWe>YQ%TY182fGcCHFJBFU0E}6o& zKN*Mc)>AgeOM;mM<5Us*L5}9p_vFFwiiitY@VH6f2(>wtkGj%Xc=mZEo$9B8SxqwJ zGe!4F-3b>2@`7*r@f=m^Y3(OqKuhTKYjoYO^>ai=lrvLnK+Xmn+m%RDxM95y7R zVDGUjgZaxOD)M`rTh@$P(=ox38|IeDGMf)-FEP&Ik3=wLj4B2x)Vi58sU)J4oy}TQ zPIO!_Kr5+R)5;(!QeaEf_R=(FGXxB&y2g|#OoFga0b~k;qre9KoHSd|`btWfoCs zS)r5s5|jtUrO9uP;=^1@bK$zhS4EhXsexf~BAznzTa8zPcT`ko)Gg5X*V3-Str>9e zmVtV)5ld>c42i3H=RZN4Ttk|bfrQ)&6APNLbZSvIM0LgTPQuOtE%#I;@$mQ)A%Z1* zAC{|4r>8WT)mW@~h3L8hx(50y)q~z8sP9?XUWV2hV|h=6Q@F%SpHrbMarhN;{r=m1 zJqt>U@g9@bQP%NNszXvwyOIcr|E7}k*4dSll#cDm4F4xAm2M59XrbOC)RP&3@Jdt9 z^ypl4$$2Yw>nZmTI{&Jg)a87z_K50C$${xg&QbQ@`+O9%@ix|7za-UPn(n`@#@k=| zp;5HD3Um)%sGWEsZ2yFL>e*>K! zF}OUZ?IDkNwP(~DSZFG{?W1wE^K7h0Q0FDS7YMw0DY9m;*R zCKeS25>wmC{7jiKsQ;L7z;$r%KgrwAZ}$}W-1g`%Tw!1!Y*i5W+98kGz%fVvd<$j* ze%|J_8~II+pTo#@!T<7Ac1qUz1oYmHkl!}^^9v?wC(vE%@+TcS4>;lKPZvo&K2zL< zjc1BM2Jxj0^k1niGcAue<-) zKFV@5O{l#>?CZ@1TYA)&e<9*zm&_7rqY&Jp=LpG&o$~*zu=Q0mpRq~y%RLsm^x+y? zhRMfsynhS8G|sn3|7S#cz$Hle?^zNG0D$-_35ovp@_!Z~OpKeA^8bI5|G}X!KWO3H%8(16VBvJ|thgTGxitAs{{{U4Tw6*{M diff --git a/csr_out/csr_dma.h b/csr_out/csr_dma.h index 7fc5b8b..d6ddbec 100644 --- a/csr_out/csr_dma.h +++ b/csr_out/csr_dma.h @@ -47,38 +47,29 @@ #define CSR_DMA_DMA_DESC_SRC_ADDR_SRC_ADDR_BIT_MASK 0xffffffff #define CSR_DMA_DMA_DESC_SRC_ADDR_SRC_ADDR_BIT_OFFSET 0 #define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_WIDTH 8 -#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_SIZE 40 +#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_SIZE 16 #define CSR_DMA_DMA_DESC_SRC_ADDR_ARRAY_DIMENSION 1 -#define CSR_DMA_DMA_DESC_SRC_ADDR_ARRAY_SIZE_0 5 +#define CSR_DMA_DMA_DESC_SRC_ADDR_ARRAY_SIZE_0 2 #define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_0 0x20 #define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_1 0x28 -#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_2 0x30 -#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_3 0x38 -#define CSR_DMA_DMA_DESC_SRC_ADDR_BYTE_OFFSET_4 0x40 #define CSR_DMA_DMA_DESC_DST_ADDR_DST_ADDR_BIT_WIDTH 32 #define CSR_DMA_DMA_DESC_DST_ADDR_DST_ADDR_BIT_MASK 0xffffffff #define CSR_DMA_DMA_DESC_DST_ADDR_DST_ADDR_BIT_OFFSET 0 #define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_WIDTH 8 -#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_SIZE 40 +#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_SIZE 16 #define CSR_DMA_DMA_DESC_DST_ADDR_ARRAY_DIMENSION 1 -#define CSR_DMA_DMA_DESC_DST_ADDR_ARRAY_SIZE_0 5 -#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_0 0x48 -#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_1 0x50 -#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_2 0x58 -#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_3 0x60 -#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_4 0x68 +#define CSR_DMA_DMA_DESC_DST_ADDR_ARRAY_SIZE_0 2 +#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_0 0x30 +#define CSR_DMA_DMA_DESC_DST_ADDR_BYTE_OFFSET_1 0x38 #define CSR_DMA_DMA_DESC_NUM_BYTES_NUM_BYTES_BIT_WIDTH 32 #define CSR_DMA_DMA_DESC_NUM_BYTES_NUM_BYTES_BIT_MASK 0xffffffff #define CSR_DMA_DMA_DESC_NUM_BYTES_NUM_BYTES_BIT_OFFSET 0 #define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_WIDTH 8 -#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_SIZE 40 +#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_SIZE 16 #define CSR_DMA_DMA_DESC_NUM_BYTES_ARRAY_DIMENSION 1 -#define CSR_DMA_DMA_DESC_NUM_BYTES_ARRAY_SIZE_0 5 -#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_0 0x70 -#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_1 0x78 -#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_2 0x80 -#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_3 0x88 -#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_4 0x90 +#define CSR_DMA_DMA_DESC_NUM_BYTES_ARRAY_SIZE_0 2 +#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_0 0x40 +#define CSR_DMA_DMA_DESC_NUM_BYTES_BYTE_OFFSET_1 0x48 #define CSR_DMA_DMA_DESC_CFG_WRITE_MODE_BIT_WIDTH 1 #define CSR_DMA_DMA_DESC_CFG_WRITE_MODE_BIT_MASK 0x1 #define CSR_DMA_DMA_DESC_CFG_WRITE_MODE_BIT_OFFSET 0 @@ -89,23 +80,32 @@ #define CSR_DMA_DMA_DESC_CFG_ENABLE_BIT_MASK 0x1 #define CSR_DMA_DMA_DESC_CFG_ENABLE_BIT_OFFSET 2 #define CSR_DMA_DMA_DESC_CFG_BYTE_WIDTH 8 -#define CSR_DMA_DMA_DESC_CFG_BYTE_SIZE 40 +#define CSR_DMA_DMA_DESC_CFG_BYTE_SIZE 16 #define CSR_DMA_DMA_DESC_CFG_ARRAY_DIMENSION 1 -#define CSR_DMA_DMA_DESC_CFG_ARRAY_SIZE_0 5 -#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_0 0x98 -#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_1 0xa0 -#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_2 0xa8 -#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_3 0xb0 -#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_4 0xb8 +#define CSR_DMA_DMA_DESC_CFG_ARRAY_SIZE_0 2 +#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_0 0x50 +#define CSR_DMA_DMA_DESC_CFG_BYTE_OFFSET_1 0x58 typedef struct { uint64_t dma_control; uint64_t dma_status; uint64_t dma_error_addr; uint64_t dma_error_stats; - uint64_t dma_desc_src_addr[5]; - uint64_t dma_desc_dst_addr[5]; - uint64_t dma_desc_num_bytes[5]; - uint64_t dma_desc_cfg[5]; + uint64_t dma_desc_src_addr[2]; + uint64_t dma_desc_dst_addr[2]; + uint64_t dma_desc_num_bytes[2]; + uint64_t dma_desc_cfg[2]; + uint64_t __reserved_0x60; + uint64_t __reserved_0x68; + uint64_t __reserved_0x70; + uint64_t __reserved_0x78; + uint64_t __reserved_0x80; + uint64_t __reserved_0x88; + uint64_t __reserved_0x90; + uint64_t __reserved_0x98; + uint64_t __reserved_0xa0; + uint64_t __reserved_0xa8; + uint64_t __reserved_0xb0; + uint64_t __reserved_0xb8; uint64_t __reserved_0xc0; uint64_t __reserved_0xc8; uint64_t __reserved_0xd0; diff --git a/csr_out/csr_dma.md b/csr_out/csr_dma.md index 5c18431..4f53aac 100644 --- a/csr_out/csr_dma.md +++ b/csr_out/csr_dma.md @@ -9,10 +9,10 @@ |[dma_status](#csr_dma-dma_status)|0x08| |[dma_error_addr](#csr_dma-dma_error_addr)|0x10| |[dma_error_stats](#csr_dma-dma_error_stats)|0x18| -|[dma_desc_src_addr[5]](#csr_dma-dma_desc_src_addr)|0x20
0x28
0x30
0x38
0x40| -|[dma_desc_dst_addr[5]](#csr_dma-dma_desc_dst_addr)|0x48
0x50
0x58
0x60
0x68| -|[dma_desc_num_bytes[5]](#csr_dma-dma_desc_num_bytes)|0x70
0x78
0x80
0x88
0x90| -|[dma_desc_cfg[5]](#csr_dma-dma_desc_cfg)|0x98
0xa0
0xa8
0xb0
0xb8| +|[dma_desc_src_addr[2]](#csr_dma-dma_desc_src_addr)|0x20
0x28| +|[dma_desc_dst_addr[2]](#csr_dma-dma_desc_dst_addr)|0x30
0x38| +|[dma_desc_num_bytes[2]](#csr_dma-dma_desc_num_bytes)|0x40
0x48| +|[dma_desc_cfg[2]](#csr_dma-dma_desc_cfg)|0x50
0x58| ###
dma_control @@ -64,14 +64,11 @@ |error_src|[1]|ro|0x0||Error source - 0 READ / 1 WRITE| |error_trig|[2]|ro|0x0||Error Trigger, asserted when error happens| -###
dma_desc_src_addr[5] +###
dma_desc_src_addr[2] * offset_address * 0x20 * 0x28 - * 0x30 - * 0x38 - * 0x40 * type * default @@ -79,14 +76,11 @@ |:--|:--|:--|:--|:--|:--| |src_addr|[31:0]|rw|0x00000000||Source address to fetch data| -###
dma_desc_dst_addr[5] +###
dma_desc_dst_addr[2] * offset_address - * 0x48 - * 0x50 - * 0x58 - * 0x60 - * 0x68 + * 0x30 + * 0x38 * type * default @@ -94,14 +88,11 @@ |:--|:--|:--|:--|:--|:--| |dst_addr|[31:0]|rw|0x00000000||Target address to write data| -###
dma_desc_num_bytes[5] +###
dma_desc_num_bytes[2] * offset_address - * 0x70 - * 0x78 - * 0x80 - * 0x88 - * 0x90 + * 0x40 + * 0x48 * type * default @@ -109,14 +100,11 @@ |:--|:--|:--|:--|:--|:--| |num_bytes|[31:0]|rw|0x00000000||Number of bytes to transfer| -###
dma_desc_cfg[5] +###
dma_desc_cfg[2] * offset_address - * 0x98 - * 0xa0 - * 0xa8 - * 0xb0 - * 0xb8 + * 0x50 + * 0x58 * type * default diff --git a/csr_out/csr_dma.sv b/csr_out/csr_dma.sv index 15861f2..91f8215 100644 --- a/csr_out/csr_dma.sv +++ b/csr_out/csr_dma.sv @@ -41,20 +41,20 @@ module csr_dma input logic i_dma_error_stats_error_type, input logic i_dma_error_stats_error_src, input logic i_dma_error_stats_error_trig, - output logic [4:0][31:0] o_dma_desc_src_addr_src_addr, - output logic [4:0][31:0] o_dma_desc_dst_addr_dst_addr, - output logic [4:0][31:0] o_dma_desc_num_bytes_num_bytes, - output logic [4:0] o_dma_desc_cfg_write_mode, - output logic [4:0] o_dma_desc_cfg_read_mode, - output logic [4:0] o_dma_desc_cfg_enable + output logic [1:0][31:0] o_dma_desc_src_addr_src_addr, + output logic [1:0][31:0] o_dma_desc_dst_addr_dst_addr, + output logic [1:0][31:0] o_dma_desc_num_bytes_num_bytes, + output logic [1:0] o_dma_desc_cfg_write_mode, + output logic [1:0] o_dma_desc_cfg_read_mode, + output logic [1:0] o_dma_desc_cfg_enable ); - rggen_register_if #(8, 64, 64) register_if[24](); + rggen_register_if #(8, 64, 64) register_if[12](); rggen_axi4lite_adapter #( .ID_WIDTH (ID_WIDTH), .ADDRESS_WIDTH (ADDRESS_WIDTH), .LOCAL_ADDRESS_WIDTH (8), .BUS_WIDTH (64), - .REGISTERS (24), + .REGISTERS (12), .PRE_DECODE (PRE_DECODE), .BASE_ADDRESS (BASE_ADDRESS), .BYTE_SIZE (256), @@ -400,7 +400,7 @@ module csr_dma end endgenerate generate if (1) begin : g_dma_desc_src_addr genvar i; - for (i = 0;i < 5;++i) begin : g + for (i = 0;i < 2;++i) begin : g rggen_bit_field_if #(64) bit_field_if(); `rggen_tie_off_unused_signals(64, 64'h00000000ffffffff, bit_field_if) rggen_default_register #( @@ -447,21 +447,21 @@ module csr_dma end endgenerate generate if (1) begin : g_dma_desc_dst_addr genvar i; - for (i = 0;i < 5;++i) begin : g + for (i = 0;i < 2;++i) begin : g rggen_bit_field_if #(64) bit_field_if(); `rggen_tie_off_unused_signals(64, 64'h00000000ffffffff, bit_field_if) rggen_default_register #( .READABLE (1), .WRITABLE (1), .ADDRESS_WIDTH (8), - .OFFSET_ADDRESS (8'h48), + .OFFSET_ADDRESS (8'h30), .BUS_WIDTH (64), .DATA_WIDTH (64), .REGISTER_INDEX (i) ) u_register ( .i_clk (i_clk), .i_rst_n (i_rst_n), - .register_if (register_if[9+i]), + .register_if (register_if[6+i]), .bit_field_if (bit_field_if) ); if (1) begin : g_dst_addr @@ -494,21 +494,21 @@ module csr_dma end endgenerate generate if (1) begin : g_dma_desc_num_bytes genvar i; - for (i = 0;i < 5;++i) begin : g + for (i = 0;i < 2;++i) begin : g rggen_bit_field_if #(64) bit_field_if(); `rggen_tie_off_unused_signals(64, 64'h00000000ffffffff, bit_field_if) rggen_default_register #( .READABLE (1), .WRITABLE (1), .ADDRESS_WIDTH (8), - .OFFSET_ADDRESS (8'h70), + .OFFSET_ADDRESS (8'h40), .BUS_WIDTH (64), .DATA_WIDTH (64), .REGISTER_INDEX (i) ) u_register ( .i_clk (i_clk), .i_rst_n (i_rst_n), - .register_if (register_if[14+i]), + .register_if (register_if[8+i]), .bit_field_if (bit_field_if) ); if (1) begin : g_num_bytes @@ -541,21 +541,21 @@ module csr_dma end endgenerate generate if (1) begin : g_dma_desc_cfg genvar i; - for (i = 0;i < 5;++i) begin : g + for (i = 0;i < 2;++i) begin : g rggen_bit_field_if #(64) bit_field_if(); `rggen_tie_off_unused_signals(64, 64'h0000000000000007, bit_field_if) rggen_default_register #( .READABLE (1), .WRITABLE (1), .ADDRESS_WIDTH (8), - .OFFSET_ADDRESS (8'h98), + .OFFSET_ADDRESS (8'h50), .BUS_WIDTH (64), .DATA_WIDTH (64), .REGISTER_INDEX (i) ) u_register ( .i_clk (i_clk), .i_rst_n (i_rst_n), - .register_if (register_if[19+i]), + .register_if (register_if[10+i]), .bit_field_if (bit_field_if) ); if (1) begin : g_write_mode diff --git a/csr_out/csr_dma.v b/csr_out/csr_dma.v index 3c89544..3a7d858 100644 --- a/csr_out/csr_dma.v +++ b/csr_out/csr_dma.v @@ -41,29 +41,29 @@ module csr_dma #( input i_dma_error_stats_error_type, input i_dma_error_stats_error_src, input i_dma_error_stats_error_trig, - output [159:0] o_dma_desc_src_addr_src_addr, - output [159:0] o_dma_desc_dst_addr_dst_addr, - output [159:0] o_dma_desc_num_bytes_num_bytes, - output [4:0] o_dma_desc_cfg_write_mode, - output [4:0] o_dma_desc_cfg_read_mode, - output [4:0] o_dma_desc_cfg_enable + output [63:0] o_dma_desc_src_addr_src_addr, + output [63:0] o_dma_desc_dst_addr_dst_addr, + output [63:0] o_dma_desc_num_bytes_num_bytes, + output [1:0] o_dma_desc_cfg_write_mode, + output [1:0] o_dma_desc_cfg_read_mode, + output [1:0] o_dma_desc_cfg_enable ); wire w_register_valid; wire [1:0] w_register_access; wire [7:0] w_register_address; wire [63:0] w_register_write_data; wire [7:0] w_register_strobe; - wire [23:0] w_register_active; - wire [23:0] w_register_ready; - wire [47:0] w_register_status; - wire [1535:0] w_register_read_data; - wire [1535:0] w_register_value; + wire [11:0] w_register_active; + wire [11:0] w_register_ready; + wire [23:0] w_register_status; + wire [767:0] w_register_read_data; + wire [767:0] w_register_value; rggen_axi4lite_adapter #( .ID_WIDTH (ID_WIDTH), .ADDRESS_WIDTH (ADDRESS_WIDTH), .LOCAL_ADDRESS_WIDTH (8), .BUS_WIDTH (64), - .REGISTERS (24), + .REGISTERS (12), .PRE_DECODE (PRE_DECODE), .BASE_ADDRESS (BASE_ADDRESS), .BYTE_SIZE (256), @@ -535,7 +535,7 @@ module csr_dma #( end endgenerate generate if (1) begin : g_dma_desc_src_addr genvar i; - for (i = 0;i < 5;i = i + 1) begin : g + for (i = 0;i < 2;i = i + 1) begin : g wire w_bit_field_valid; wire [63:0] w_bit_field_read_mask; wire [63:0] w_bit_field_write_mask; @@ -603,7 +603,7 @@ module csr_dma #( end endgenerate generate if (1) begin : g_dma_desc_dst_addr genvar i; - for (i = 0;i < 5;i = i + 1) begin : g + for (i = 0;i < 2;i = i + 1) begin : g wire w_bit_field_valid; wire [63:0] w_bit_field_read_mask; wire [63:0] w_bit_field_write_mask; @@ -615,7 +615,7 @@ module csr_dma #( .READABLE (1), .WRITABLE (1), .ADDRESS_WIDTH (8), - .OFFSET_ADDRESS (8'h48), + .OFFSET_ADDRESS (8'h30), .BUS_WIDTH (64), .DATA_WIDTH (64), .REGISTER_INDEX (i) @@ -627,11 +627,11 @@ module csr_dma #( .i_register_address (w_register_address), .i_register_write_data (w_register_write_data), .i_register_strobe (w_register_strobe), - .o_register_active (w_register_active[1*(9+i)+:1]), - .o_register_ready (w_register_ready[1*(9+i)+:1]), - .o_register_status (w_register_status[2*(9+i)+:2]), - .o_register_read_data (w_register_read_data[64*(9+i)+:64]), - .o_register_value (w_register_value[64*(9+i)+0+:64]), + .o_register_active (w_register_active[1*(6+i)+:1]), + .o_register_ready (w_register_ready[1*(6+i)+:1]), + .o_register_status (w_register_status[2*(6+i)+:2]), + .o_register_read_data (w_register_read_data[64*(6+i)+:64]), + .o_register_value (w_register_value[64*(6+i)+0+:64]), .o_bit_field_valid (w_bit_field_valid), .o_bit_field_read_mask (w_bit_field_read_mask), .o_bit_field_write_mask (w_bit_field_write_mask), @@ -671,7 +671,7 @@ module csr_dma #( end endgenerate generate if (1) begin : g_dma_desc_num_bytes genvar i; - for (i = 0;i < 5;i = i + 1) begin : g + for (i = 0;i < 2;i = i + 1) begin : g wire w_bit_field_valid; wire [63:0] w_bit_field_read_mask; wire [63:0] w_bit_field_write_mask; @@ -683,7 +683,7 @@ module csr_dma #( .READABLE (1), .WRITABLE (1), .ADDRESS_WIDTH (8), - .OFFSET_ADDRESS (8'h70), + .OFFSET_ADDRESS (8'h40), .BUS_WIDTH (64), .DATA_WIDTH (64), .REGISTER_INDEX (i) @@ -695,11 +695,11 @@ module csr_dma #( .i_register_address (w_register_address), .i_register_write_data (w_register_write_data), .i_register_strobe (w_register_strobe), - .o_register_active (w_register_active[1*(14+i)+:1]), - .o_register_ready (w_register_ready[1*(14+i)+:1]), - .o_register_status (w_register_status[2*(14+i)+:2]), - .o_register_read_data (w_register_read_data[64*(14+i)+:64]), - .o_register_value (w_register_value[64*(14+i)+0+:64]), + .o_register_active (w_register_active[1*(8+i)+:1]), + .o_register_ready (w_register_ready[1*(8+i)+:1]), + .o_register_status (w_register_status[2*(8+i)+:2]), + .o_register_read_data (w_register_read_data[64*(8+i)+:64]), + .o_register_value (w_register_value[64*(8+i)+0+:64]), .o_bit_field_valid (w_bit_field_valid), .o_bit_field_read_mask (w_bit_field_read_mask), .o_bit_field_write_mask (w_bit_field_write_mask), @@ -739,7 +739,7 @@ module csr_dma #( end endgenerate generate if (1) begin : g_dma_desc_cfg genvar i; - for (i = 0;i < 5;i = i + 1) begin : g + for (i = 0;i < 2;i = i + 1) begin : g wire w_bit_field_valid; wire [63:0] w_bit_field_read_mask; wire [63:0] w_bit_field_write_mask; @@ -751,7 +751,7 @@ module csr_dma #( .READABLE (1), .WRITABLE (1), .ADDRESS_WIDTH (8), - .OFFSET_ADDRESS (8'h98), + .OFFSET_ADDRESS (8'h50), .BUS_WIDTH (64), .DATA_WIDTH (64), .REGISTER_INDEX (i) @@ -763,11 +763,11 @@ module csr_dma #( .i_register_address (w_register_address), .i_register_write_data (w_register_write_data), .i_register_strobe (w_register_strobe), - .o_register_active (w_register_active[1*(19+i)+:1]), - .o_register_ready (w_register_ready[1*(19+i)+:1]), - .o_register_status (w_register_status[2*(19+i)+:2]), - .o_register_read_data (w_register_read_data[64*(19+i)+:64]), - .o_register_value (w_register_value[64*(19+i)+0+:64]), + .o_register_active (w_register_active[1*(10+i)+:1]), + .o_register_ready (w_register_ready[1*(10+i)+:1]), + .o_register_status (w_register_status[2*(10+i)+:2]), + .o_register_read_data (w_register_read_data[64*(10+i)+:64]), + .o_register_value (w_register_value[64*(10+i)+0+:64]), .o_bit_field_valid (w_bit_field_valid), .o_bit_field_read_mask (w_bit_field_read_mask), .o_bit_field_write_mask (w_bit_field_write_mask), diff --git a/csr_out/csr_dma_ral_pkg.sv b/csr_out/csr_dma_ral_pkg.sv index 3d687e4..94d2a75 100644 --- a/csr_out/csr_dma_ral_pkg.sv +++ b/csr_out/csr_dma_ral_pkg.sv @@ -96,10 +96,10 @@ package csr_dma_ral_pkg; rand dma_status_reg_model dma_status; rand dma_error_addr_reg_model dma_error_addr; rand dma_error_stats_reg_model dma_error_stats; - rand dma_desc_src_addr_reg_model dma_desc_src_addr[5]; - rand dma_desc_dst_addr_reg_model dma_desc_dst_addr[5]; - rand dma_desc_num_bytes_reg_model dma_desc_num_bytes[5]; - rand dma_desc_cfg_reg_model dma_desc_cfg[5]; + rand dma_desc_src_addr_reg_model dma_desc_src_addr[2]; + rand dma_desc_dst_addr_reg_model dma_desc_dst_addr[2]; + rand dma_desc_num_bytes_reg_model dma_desc_num_bytes[2]; + rand dma_desc_cfg_reg_model dma_desc_cfg[2]; function new(string name); super.new(name, 8, 0); endfunction @@ -110,24 +110,12 @@ package csr_dma_ral_pkg; `rggen_ral_create_reg(dma_error_stats, '{}, 8'h18, "RO", "g_dma_error_stats.u_register") `rggen_ral_create_reg(dma_desc_src_addr[0], '{0}, 8'h20, "RW", "g_dma_desc_src_addr.g[0].u_register") `rggen_ral_create_reg(dma_desc_src_addr[1], '{1}, 8'h28, "RW", "g_dma_desc_src_addr.g[1].u_register") - `rggen_ral_create_reg(dma_desc_src_addr[2], '{2}, 8'h30, "RW", "g_dma_desc_src_addr.g[2].u_register") - `rggen_ral_create_reg(dma_desc_src_addr[3], '{3}, 8'h38, "RW", "g_dma_desc_src_addr.g[3].u_register") - `rggen_ral_create_reg(dma_desc_src_addr[4], '{4}, 8'h40, "RW", "g_dma_desc_src_addr.g[4].u_register") - `rggen_ral_create_reg(dma_desc_dst_addr[0], '{0}, 8'h48, "RW", "g_dma_desc_dst_addr.g[0].u_register") - `rggen_ral_create_reg(dma_desc_dst_addr[1], '{1}, 8'h50, "RW", "g_dma_desc_dst_addr.g[1].u_register") - `rggen_ral_create_reg(dma_desc_dst_addr[2], '{2}, 8'h58, "RW", "g_dma_desc_dst_addr.g[2].u_register") - `rggen_ral_create_reg(dma_desc_dst_addr[3], '{3}, 8'h60, "RW", "g_dma_desc_dst_addr.g[3].u_register") - `rggen_ral_create_reg(dma_desc_dst_addr[4], '{4}, 8'h68, "RW", "g_dma_desc_dst_addr.g[4].u_register") - `rggen_ral_create_reg(dma_desc_num_bytes[0], '{0}, 8'h70, "RW", "g_dma_desc_num_bytes.g[0].u_register") - `rggen_ral_create_reg(dma_desc_num_bytes[1], '{1}, 8'h78, "RW", "g_dma_desc_num_bytes.g[1].u_register") - `rggen_ral_create_reg(dma_desc_num_bytes[2], '{2}, 8'h80, "RW", "g_dma_desc_num_bytes.g[2].u_register") - `rggen_ral_create_reg(dma_desc_num_bytes[3], '{3}, 8'h88, "RW", "g_dma_desc_num_bytes.g[3].u_register") - `rggen_ral_create_reg(dma_desc_num_bytes[4], '{4}, 8'h90, "RW", "g_dma_desc_num_bytes.g[4].u_register") - `rggen_ral_create_reg(dma_desc_cfg[0], '{0}, 8'h98, "RW", "g_dma_desc_cfg.g[0].u_register") - `rggen_ral_create_reg(dma_desc_cfg[1], '{1}, 8'ha0, "RW", "g_dma_desc_cfg.g[1].u_register") - `rggen_ral_create_reg(dma_desc_cfg[2], '{2}, 8'ha8, "RW", "g_dma_desc_cfg.g[2].u_register") - `rggen_ral_create_reg(dma_desc_cfg[3], '{3}, 8'hb0, "RW", "g_dma_desc_cfg.g[3].u_register") - `rggen_ral_create_reg(dma_desc_cfg[4], '{4}, 8'hb8, "RW", "g_dma_desc_cfg.g[4].u_register") + `rggen_ral_create_reg(dma_desc_dst_addr[0], '{0}, 8'h30, "RW", "g_dma_desc_dst_addr.g[0].u_register") + `rggen_ral_create_reg(dma_desc_dst_addr[1], '{1}, 8'h38, "RW", "g_dma_desc_dst_addr.g[1].u_register") + `rggen_ral_create_reg(dma_desc_num_bytes[0], '{0}, 8'h40, "RW", "g_dma_desc_num_bytes.g[0].u_register") + `rggen_ral_create_reg(dma_desc_num_bytes[1], '{1}, 8'h48, "RW", "g_dma_desc_num_bytes.g[1].u_register") + `rggen_ral_create_reg(dma_desc_cfg[0], '{0}, 8'h50, "RW", "g_dma_desc_cfg.g[0].u_register") + `rggen_ral_create_reg(dma_desc_cfg[1], '{1}, 8'h58, "RW", "g_dma_desc_cfg.g[1].u_register") endfunction endclass endpackage diff --git a/rtl/dma_streamer.sv b/rtl/dma_streamer.sv index 76e700e..9beef8f 100644 --- a/rtl/dma_streamer.sv +++ b/rtl/dma_streamer.sv @@ -25,7 +25,7 @@ module dma_streamer output s_dma_str_out_t dma_stream_o ); localparam bytes_p_burst = (`DMA_DATA_WIDTH/8); - localparam max_txn_width = $clog2(256*(`DMA_DATA_WIDTH/8)); + localparam max_txn_width = $clog2(`DMA_MAX_BEAT_BURST*(`DMA_DATA_WIDTH/8)); dma_sm_t cur_st_ff, next_st; axi_addr_t desc_addr_ff, next_desc_addr; @@ -68,12 +68,13 @@ module dma_streamer endcase end - for (logic [3:0] i=0; i<8; i++) begin - if (addr == i[2:0]) begin - strobe = strobe << i; + if (`DMA_EN_UNALIGNED) begin + for (logic [3:0] i=0; i<8; i++) begin + if (addr == i[2:0]) begin + strobe = strobe << i; + end end end - return strobe; endfunction @@ -141,13 +142,13 @@ module dma_streamer axi_alen_t alen = 0; // Single beat-burst desc_num_t txn_sz; - for (int i=256; i>0; i--) begin + for (int i=`DMA_MAX_BEAT_BURST; i>0; i--) begin // Check if we have enough bytes for this alen and that if // it is less or equal than the max burst configured in the // CSRs and the burst mode fut_addr = addr+(i*bytes_p_burst); txn_sz = (i*bytes_p_burst); - if ((bytes >= txn_sz) && ((i-'d1) <= dma_maxb_i) && valid_burst(dma_mode_ff, i[8:0])) begin + if ((bytes >= txn_sz) && ((`DMA_MAX_BURST_EN == 1) ? ((i-'d1) <= dma_maxb_i) : 1'b1) && ((`DMA_MAX_BEAT_BURST > 16) ? valid_burst(dma_mode_ff, i[8:0]) : 1'b1)) begin // Check if we respect the 4KB boundary per burst if (burst_r4KB(addr, fut_addr)) begin alen = axi_alen_t'(i-1); @@ -237,18 +238,24 @@ module dma_streamer else begin next_dma_req.alen = axi_alen_t'('0); // Three possible cases here, beginning, end of processing or small descriptor - if (enough_for_burst(desc_bytes_ff)) begin // Beginning unaligned - num_unalign_bytes = bytes_to_align(desc_addr_ff); - next_dma_req.strb = get_strb(desc_addr_ff[2:0], num_unalign_bytes); + if (`DMA_EN_UNALIGNED) begin + if (enough_for_burst(desc_bytes_ff)) begin // Beginning unaligned + num_unalign_bytes = bytes_to_align(desc_addr_ff); + next_dma_req.strb = get_strb(desc_addr_ff[2:0], num_unalign_bytes); + end + else if (is_aligned(desc_addr_ff)) begin // Now it's aligned but not enough bytes, end of processing + num_unalign_bytes = desc_bytes_ff[3:0]; + next_dma_req.strb = get_strb('d0, num_unalign_bytes); + end + else begin // Small descriptor + num_unalign_bytes = desc_bytes_ff[3:0]; + next_dma_req.strb = get_strb(desc_addr_ff[2:0], num_unalign_bytes); + end end - else if (is_aligned(desc_addr_ff)) begin // Now it's aligned but not enough bytes, end of processing + else begin num_unalign_bytes = desc_bytes_ff[3:0]; next_dma_req.strb = get_strb('d0, num_unalign_bytes); end - else begin // Small descriptor - num_unalign_bytes = desc_bytes_ff[3:0]; - next_dma_req.strb = get_strb(desc_addr_ff[2:0], num_unalign_bytes); - end end /* verilator lint_off WIDTH */ txn_bytes = full_burst ? max_bytes_t'((next_dma_req.alen+8'd1)*bytes_p_burst) : diff --git a/rtl/inc/dma_pkg.svh b/rtl/inc/dma_pkg.svh index 865e831..af0e9ba 100644 --- a/rtl/inc/dma_pkg.svh +++ b/rtl/inc/dma_pkg.svh @@ -6,40 +6,52 @@ // xls sheet to generate the same // correspondent number of desc `ifndef DMA_NUM_DESC - `define DMA_NUM_DESC 5 + `define DMA_NUM_DESC 2 `endif `ifndef DMA_ADDR_WIDTH - `define DMA_ADDR_WIDTH `AXI_ADDR_WIDTH + `define DMA_ADDR_WIDTH `AXI_ADDR_WIDTH `endif `ifndef DMA_DATA_WIDTH - `define DMA_DATA_WIDTH `AXI_DATA_WIDTH + `define DMA_DATA_WIDTH `AXI_DATA_WIDTH `endif `ifndef DMA_BYTES_WIDTH - `define DMA_BYTES_WIDTH 32 + `define DMA_BYTES_WIDTH 32 `endif `ifndef DMA_RD_TXN_BUFF - `define DMA_RD_TXN_BUFF 8 // Must be power of 2 + `define DMA_RD_TXN_BUFF 8 // Must be power of 2 `endif `ifndef DMA_WR_TXN_BUFF - `define DMA_WR_TXN_BUFF 8 // Must be power of 2 + `define DMA_WR_TXN_BUFF 8 // Must be power of 2 `endif // FIFO size in bytes = (DMA_FIFO_DEPTH*(AXI_DATA_WIDTH/8)) `ifndef DMA_FIFO_DEPTH - `define DMA_FIFO_DEPTH 16 // Must be power of 2 + `define DMA_FIFO_DEPTH 16 // Must be power of 2 `endif `ifndef DMA_ID_WIDTH - `define DMA_ID_WIDTH `AXI_TXN_ID_WIDTH + `define DMA_ID_WIDTH `AXI_TXN_ID_WIDTH `endif `ifndef DMA_ID_VAL - `define DMA_ID_VAL 0 + `define DMA_ID_VAL 0 + `endif + + `ifndef DMA_MAX_BEAT_BURST + `define DMA_MAX_BEAT_BURST 256 // 1 up to 256 + `endif + + `ifndef DMA_EN_UNALIGNED + `define DMA_EN_UNALIGNED 1 + `endif + + `ifndef DMA_MAX_BURST_EN + `define DMA_MAX_BURST_EN 1 `endif localparam FIFO_WIDTH = $clog2(`DMA_FIFO_DEPTH>1?`DMA_FIFO_DEPTH:2); diff --git a/tb/common/constants.py b/tb/common/constants.py index 079063a..d58a074 100644 --- a/tb/common/constants.py +++ b/tb/common/constants.py @@ -4,7 +4,7 @@ # License : MIT license # Author : Anderson Ignacio da Silva (aignacio) # Date : 03.06.2022 -# Last Modified Date: 14.10.2022 +# Last Modified Date: 16.10.2022 import os import glob import copy @@ -12,7 +12,7 @@ class cfg_const: ################### Start Configure #################### - regression_setup = ['32', '64'] + regression_setup = ['32', '64','small'] RST_CYCLES = 3 TIMEOUT_VAL = 20000 @@ -24,13 +24,19 @@ class cfg_const: DMA_CFG_64b['axi_addr_width'] = 32 DMA_CFG_64b['axi_data_width'] = 64 + DMA_CFG_SMALL = {} + DMA_CFG_SMALL['axi_addr_width'] = 32 + DMA_CFG_SMALL['axi_data_width'] = 32 + DMA_CFG_SMALL['dma_max_beat_burst'] = 8 + DMA_CFG_SMALL['dma_en_unaligned'] = 0 + DMA_CSRs = {} #-------------------------------> Addr Mask RW DMA_CSRs['DMA_CONTROL'] = (0x0000, 0x3FF, 1) DMA_CSRs['DMA_STATUS'] = (0x0008, 0xCAFE, 0) DMA_CSRs['DMA_ERROR_ADDR'] = (0x0010, 0x0, 0) DMA_CSRs['DMA_ERROR_MISC'] = (0x0018, 0x0, 0) - NUM_DESC = 5 + NUM_DESC = 2 PER_DESC_CSRS = 4 CSR_ADDR_ALIG = 8 BASE_ADDR_DESC = 0x20 @@ -77,14 +83,18 @@ class cfg_const: EXTRA_ARGS_32b = copy.deepcopy(EXTRA_ARGS) EXTRA_ARGS_64b = copy.deepcopy(EXTRA_ARGS) + EXTRA_ARGS_SMALL = copy.deepcopy(EXTRA_ARGS) for param in DMA_CFG_32b.items(): EXTRA_ARGS_32b.append("-D"+param[0].upper()+"="+str(param[1])) for param in DMA_CFG_64b.items(): EXTRA_ARGS_64b.append("-D"+param[0].upper()+"="+str(param[1])) + for param in DMA_CFG_SMALL.items(): + EXTRA_ARGS_SMALL.append("-D"+param[0].upper()+"="+str(param[1])) EXTRA_ARGS_32b.append("-DRGGEN_NAIVE_MUX_IMPLEMENTATION") EXTRA_ARGS_64b.append("-DRGGEN_NAIVE_MUX_IMPLEMENTATION") + EXTRA_ARGS_SMALL.append("-DRGGEN_NAIVE_MUX_IMPLEMENTATION") def _get_cfg_args(flavor): if flavor == "32": @@ -92,4 +102,4 @@ def _get_cfg_args(flavor): elif flavor == "64": return cfg_const.EXTRA_ARGS_64b else: - return cfg_const.EXTRA_ARGS_64b + return cfg_const.EXTRA_ARGS_SMALL diff --git a/tb/common/testbench.py b/tb/common/testbench.py index ec3772c..54c3558 100644 --- a/tb/common/testbench.py +++ b/tb/common/testbench.py @@ -4,7 +4,7 @@ # License : MIT license # Author : Anderson Ignacio da Silva (aignacio) # Date : 04.06.2022 -# Last Modified Date: 20.06.2022 +# Last Modified Date: 16.10.2022 # Last Modified By : Anderson Ignacio da Silva (aignacio) import cocotb import os, errno @@ -26,9 +26,9 @@ def __init__(self, dut, log_name, cfg, flavor, ram_size=(2**12)): self.dut = dut self.cfg = cfg self.flavor = flavor - self.bb = 4 if flavor == '32' else 8 # Number of bytes per data bus lane + self.bb = 4 if flavor == '32' or flavor == 'small' else 8 # Number of bytes per data bus lane self.max_addr = ((2**32)-1) - self.max_data = ((2**32)-1) if flavor == '32' else ((2**64)-1) + self.max_data = ((2**32)-1) if flavor == '32' or flavor == 'small' else ((2**64)-1) timenow_wstamp = self._gen_log(log_name) self.maxb = 255 self.log.info("------------[LOG - %s]------------",timenow_wstamp) diff --git a/tb/test_dma_error.py b/tb/test_dma_error.py index 8734e9e..b120a78 100644 --- a/tb/test_dma_error.py +++ b/tb/test_dma_error.py @@ -4,7 +4,7 @@ # License : MIT license # Author : Anderson Ignacio da Silva (aignacio) # Date : 03.06.2022 -# Last Modified Date: 20.06.2022 +# Last Modified Date: 16.10.2022 # Last Modified By : Anderson Ignacio da Silva (aignacio) import random import cocotb @@ -41,6 +41,8 @@ async def run_test(dut, config_clk="100MHz", idle_inserter=None, backpressure_in await tb.setup_clks(config_clk) await tb.rst(config_clk) + if (dma_flavor == "small"): + return True #------------ Init test ------------# bb = sim_settings['bb'] max_data = sim_settings['max_data'] diff --git a/tb/test_dma_unaligned.py b/tb/test_dma_unaligned.py index ce85c9e..17a96c4 100644 --- a/tb/test_dma_unaligned.py +++ b/tb/test_dma_unaligned.py @@ -4,7 +4,7 @@ # License : MIT license # Author : Anderson Ignacio da Silva (aignacio) # Date : 03.06.2022 -# Last Modified Date: 21.06.2022 +# Last Modified Date: 16.10.2022 # Last Modified By : Anderson Ignacio da Silva (aignacio) import random import cocotb @@ -40,6 +40,8 @@ async def run_test(dut, config_clk="100MHz", idle_inserter=None, backpressure_in await tb.setup_clks(config_clk) await tb.rst(config_clk) + if (dma_flavor == "small"): + return True #------------ Init test ------------# bb = sim_settings['bb'] max_data = sim_settings['max_data'] diff --git a/tox.ini b/tox.ini index 142dc61..72bc57a 100644 --- a/tox.ini +++ b/tox.ini @@ -22,7 +22,7 @@ deps = cocotb-test cocotb -commands = pytest -rP -n auto {posargs} +commands = pytest -n auto {posargs} #pytest -rP -n auto {posargs} [pytest]