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chip_sim.core
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chip_sim.core
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CAPI=2:
# Copyright lowRISC contributors (OpenTitan project).
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0
name: "lowrisc:dv:chip_sim:0.1"
description: "Earlgrey chip DV sim target"
filesets:
files_rtl:
depend:
- "!gatelevel ? (lowrisc:systems:top_earlgrey)"
- lowrisc:systems:top_earlgrey_pkg
- "!gatelevel ? (lowrisc:systems:chip_earlgrey_asic)"
- lowrisc:ibex:ibex_tracer
file_type: systemVerilogSource
files_dv:
depend:
# Place the autogen packages first to avoid conflicts
- lowrisc:opentitan:top_earlgrey_alert_handler_reg
- lowrisc:opentitan:top_earlgrey_pwrmgr_pkg
- lowrisc:ip:tlul
- lowrisc:dv:chip_test
- lowrisc:dv:clkmgr_sva
- lowrisc:dv:pwrmgr_sva
- lowrisc:dv:rstmgr_sva
- lowrisc:dv:top_earlgrey_sva
- lowrisc:dv:top_earlgrey_xbar_main_bind
- lowrisc:dv:top_earlgrey_xbar_peri_bind
- lowrisc:dv:xbar_test
- lowrisc:dv:xbar_macros
- lowrisc:dv:sim_sram
- lowrisc:dv:sw_test_status
- lowrisc:dv:sw_logger_if
- lowrisc:dv:mem_bkdr_util
- lowrisc:dv_dpi_c:gpiodpi
- lowrisc:dv_dpi_sv:gpiodpi
- lowrisc:dv_dpi_c:uartdpi
- lowrisc:dv_dpi_sv:uartdpi
- lowrisc:dv_dpi_c:usbdpi
- lowrisc:dv_dpi_sv:usbdpi
- lowrisc:dv:usb20_usbdpi
files:
- tb/chip_hier_macros.svh: {is_include_file: true}
- autogen/tb__xbar_connect.sv: {is_include_file: true}
- autogen/xbar_env_pkg__params.sv: {is_include_file: true}
- autogen/tb__alert_handler_connect.sv: {is_include_file: true}
- tb/tb.sv
file_type: systemVerilogSource
files_veriblelint_waiver:
files:
- lint/chip_sim.vbw
file_type: veribleLintWaiver
targets:
default: &default_target
toplevel: tb
filesets:
- tool_veriblelint ? (files_veriblelint_waiver)
- files_rtl
- files_dv
sim:
<<: *default_target
default_tool: vcs
lint:
<<: *default_target